Отправлено Yuriy 25 мая 2003 г. 19:30 В ответ на: Ответ: А вот вопросик.... отправлено command.com 25 мая 2003 г. 14:16

http://e-www.motorola.com/brdata/PDFDB/docs/MC68HC912D60A.pdf

14.3.2 Pulse Accumulators
There are four 8-bit pulse accumulators with four 8-bit holding registers associated with the four IC buffered channels. A pulse accumulator counts the number of active edges at the input of its channel. The user can prevent 8-bit pulse accumulators counting further than $FF by PACMX control bit in ICSYS ($AB). In this case a value of $FF means that 255 counts or more have occurred.
Each pair of pulse accumulators can be used as a 16-bit pulse
accumulator.

There are two modes of operation for the pulse accumulators.

14.3.2.1 Pulse Accumulator latch mode

The value of the pulse accumulator is transferred to its holding register when the modulus down-counter reaches zero, a write $0000 to the modulus counter or when the force latch control bit ICLAT is written. At the same time the pulse accumulator is cleared.

14.3.2.2 Pulse Accumulator queue mode

When queue mode is enabled, reads of an input capture holding register
will transfer the contents of the associated pulse accumulator to its
holding register.