.macro begin
.cseg
.org 0
; ***** INTERRUPT VECTORS ************************************************
jmp start ; Reset Handler
jmp start ;INT0 ; External Interrupt0 Handler
jmp start ;INT1 ; External Interrupt1 Handler
jmp start ;TIM1_CAPT ; Timer1 Capture Handler
jmp start ;TIM1_COMPA ; Timer1 CompareA Handler
jmp start ;TIM1_OVF ; Timer1 Overflow Handler
jmp start ;TIM0_OVF ; Timer0 Overflow Handler
jmp USART0_RXC ; USART0 RX Complete Handler
jmp USART0_DRE ; USART0,UDR Empty Handler
jmp start ;USART0_TXC ; USART0 TX Complete Handler
jmp start ;ANA_COMP ; Analog Comparator Handler
jmp start ;PCINT ; Pin Change Interrupt
jmp start ;TIMER1_COMPB ; Timer1 Compare B Handler
jmp TIMER0_COMPA ; Timer0 Compare A Handler
jmp start ;TIMER0_COMPB ; Timer0 Compare B Handler
jmp start ;USI_START ; Usi Start Handler
jmp start ;USI_OVERFLOW ; USI Overflow Handler
jmp start ;EE_READY ; EEPROM Ready Handler
jmp start ;WDT_OVERFLOW ; Watchdog Overflow Handler
;
start:
ldi r16, low(RAMEND)
out spl, r16
ldi r16, 0b10000000 ; PUD=1
out MCUCR, r16
ldi r16, 0b11111111
out ddra, r16
ldi r16, 0b11111111
out porta, r16
ldi r16, 0b11111111
out ddrb, r16
ldi r16, 0b11111111
out portb, r16
ldi r16, 0b11111111
out ddrd, r16
ldi r16, 0b11111111
out portd, r16
ldi r16, (1<<SE)|(0<<SM0)|(0<<SM1)
out MCUCR, r16
in temp, TCCR0B
cbr temp, (1<<CS02)|(1<<CS00)
sbr temp, (1<<CS01)
cbr temp, (1<<WGM02)
out TCCR0B, temp
in temp, TCCR0A
cbr temp, (1<<WGM00)
sbr temp, (1<<WGM01)
out TCCR0A, temp
ldi temp, 50
out OCR0A, temp
in temp, TIMSK
sbr temp, (1<<OCIE0A) out TIMSK, temp
sei
.endmacro
************************;
.macro cport
sbic portD, 6
rjmp analog1
sbi portD, 6
rjmp analog2
analog1:
cbi portD, 6
analog2:
.endmacro
;**********************
m0:
sleep
rjmp m0
;*********************************
TIMER0_COMPA:
cport
reti
USART0_RXC:
reti
USART0_DRE:
reti