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As a Counter, the register is incremented in response to a lto-
0 transition at its corresponding external input pin, T0,
T1, or (in the AT89C52) T2. The external input is sampled
during S5P2 of every machine cycle. When the samples
show a high in one cycle and a low in the next cycle, the
count is incremented. The new count value appears in the
register during S3P1 of the cycle following the one in which
the transition was detected. Since 2 machine cycles (24
oscillator periods) are required to recognize a l-to-0 transition,
the maximum count rate is 1/24 of the oscillator frequency.
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