ISR(TIMER0_COMPA_vect)
{
switch(Phase)
{
case 0:
OCR0A += 0x40;
PORTB |= 0x80;
break;
case 1:
TIMSK0 &= ~0x02; // Timer0 Interrupt(s) OCIE0A not enabled
PORTB &= ~0x80;
break;
}
Phase++;
}