 Разработка, производство и продажа радиоэлектронной аппаратуры  |
Требуется программист в Зеленограде
- обработка данных с датчиков; ColdFire; 40 тыс. e-mail:jobsmp@pochta.ru |
/****************************************************************************
** - iotiny85.h -
**
** This file declares the internal register addresses for ATtiny85.
**
** Used with iccAVR and aAVR.
**
** Copyright IAR Systems 2005. All rights reserved.
**
** File version: $Revision: 1.7 $
**
***************************************************************************/
#ifdef __IAR_SYSTEMS_ICC__
#ifndef _SYSTEM_BUILD
#pragma system_include
#endif
#endif
#include "iomacro.h"
#if TID_GUARD(1)
#error This file should only be compiled with iccavr or aavr with processor option -v1
#endif /* TID_GUARD(1) */
/* Include the SFR part if this file has not been included before,
* OR this file is included by the assembler (SFRs must be defined in
* each assembler module). */
#if !defined(__IOTINY85_H) || defined(__IAR_SYSTEMS_ASM__)
#pragma language=extended
/*==========================*/
/* Predefined SFR Addresses */
/*==========================*/
/****************************************************************************
* An example showing the SFR_B() macro call,
* the expanded result and usage of this result:
*
* SFR_B_R(0x1F, AVR) Expands to:
* __io union {
* unsigned char AVR; // The sfrb as 1 byte
* struct { // The sfrb as 8 bits
* unsigned char AVR_Bit0:1,
* AVR_Bit1:1,
* AVR_Bit2:1,
* AVR_Bit3:1,
* AVR_Bit4:1,
* AVR_Bit5:1,
* AVR_Bit6:1,
* AVR_Bit7:1;
* };
* } @ 0x1F;
* Examples of how to use the expanded result:
* AVR |= (1<<5);
* or like this:
* AVR_Bit5 = 1;
*
*
*
* An example showing the SFR_B_N() macro call,
* the expanded result and usage of this result:
* SFR_B_N(0x25, TCCR2, FOC2, WGM20, COM21, COM20, WGM21, CS22, CS21, CS20)
* Expands to:
* __io union {
* unsigned char TCCR2;
* struct {
* unsigned char TCCR2_Bit0:1,
* TCCR2_Bit1:1,
* TCCR2_Bit2:1,
* TCCR2_Bit3:1,
* TCCR2_Bit4:1,
* TCCR2_Bit5:1,
* TCCR2_Bit6:1,
* TCCR2_Bit7:1;
* };
* struct {
* unsigned char TCCR2_CS20:1,
* TCCR2_CS21:1,
* TCCR2_CS22:1,
* TCCR2_WGM21:1,
* TCCR2_COM20:1,
* TCCR2_COM21:1,
* TCCR2_WGM20:1,
* TCCR2_FOC2:1;
* };
* } @ 0x25;
* Examples of how to use the expanded result:
* TCCR2 |= (1<<5);
* or if ENABLE_BIT_DEFINITIONS is defined
* TCCR2 |= (1<<COM21);
* or like this:
* TCCR2_Bit5 = 1;
* or like this:
* TCCR2_COM21 = 1;
***************************************************************************/
SFR_B_N(0x3F, SREG, I, T, H, S, V, N, Z, C)
SFR_W_N(0x3E, SP, Dummy15, Dummy14, Dummy13, Dummy12, Dummy11, Dummy10, Dummy9, SP8, SP7, SP6, SP5, SP4, SP3, SP2, SP1, SP0)
SFR_B_N(0x3B, GIMSK, Dummy7, INT0, PCIE, Dummy4, Dummy3, Dummy2, Dummy1, Dummy0)
SFR_B_N(0x3A, GIFR, Dummy7, INTF0, PCIF, Dummy4, Dummy3, Dummy2, Dummy1, Dummy0)
SFR_B_N(0x39, TIMSK, Dummy7, OCIE1A, OCIE1B, OCIE0A, OCIE0B, TOIE1, TOIE0, Dummy0)
SFR_B_N(0x38, TIFR, Dummy7, OCF1A, OCF1B, OCF0A, OCF0B, TOV1, TOV0, Dummy0)
SFR_B_N(0x37, SPMCSR, Dummy7, Dummy6, Dummy5, CTPB, RFLB, PGWRT, PGERS, SPMEN)
SFR_B_N(0x35, MCUCR, Dummy7, PUD, SE, SM1, SM0, Dummy2, ISC01, ISC00)
SFR_B_N(0x34, MCUSR, Dummy7, Dummy6, Dummy5, Dummy4, WDRF, BORF, EXTRF, PORF)
SFR_B_N(0x33, TCCR0B, FOC0A, FOC0B, Dummy5, Dummy4, WGM02, CS02, CS01, CS00)
SFR_B_R(0x32, TCNT0)
SFR_B_R(0x31, OSCCAL)
SFR_B_N(0x30, TCCR1, CTC1, PWM1A, COM1A1, COM1A0, CS13, CS12, CS11, CS10)
SFR_B_R(0x2F, TCNT1)
SFR_B_R(0x2E, OCR1A)
SFR_B_R(0x2D, OCR1C)
SFR_B_N(0x2C, GTCCR, TSM, PWM1B, COM1B1, COM1B0, FOC1B, FOC1A, PSR1, PSR0)
SFR_B_R(0x2B, OCR1B)
SFR_B_N(0x2A, TCCR0A, COM0A1, COM0A0, COM0B1, COM0B0, Dummy3, Dummy2, WGM01, WGM00)
SFR_B_R(0x29, OCR0A)
SFR_B_R(0x28, OCR0B)
SFR_B_N(0x27, PLLCSR, SM, Dummy6, Dummy5, Dummy4, Dummy3, PCKE, PLLE, PLOCK)
SFR_B_N(0x26, CLKPR, CLKPCE, Dummy6, Dummy5, Dummy4, CLKPS3, CLKPS2, CLKPS1, CLKPS0)
SFR_B_N(0x25, DT1A, DT1AH3, DT1AH2, DT1AH1, DT1AH0, DT1AL3, DT1AL2, DT1AL1, DT1AL0)
SFR_B_N(0x24, DT1B, DT1BH3, DT1BH2, DT1BH1, DT1BH0, DT1BL3, DT1BL2, DT1BL1, DT1BL0)
SFR_B_N(0x23, DTPS, Dummy7, Dummy6, Dummy5, Dummy4, Dummy3, Dummy2, DTPS1, DTPS0)
SFR_B_R(0x22, DWDR)
SFR_B_N(0x21, WDTCR, WDTIF, WDTIE, WDP3, WDCE, WDE, WDP2, WDP1, WDP0)
SFR_B_N(0x20, PRR, Dummy7, Dummy6, Dummy5, Dummy4, PRTIM1, PRTIM0, PRUSI, PRADC)
SFR_W_N(0x1E, EEAR, Dummy15, Dummy14, Dummy13, Dummy12, Dummy11, Dummy10, Dummy9, EEAR8, EEAR7, EEAR6, EEAR5, EEAR4, EEAR3, EEAR2, EEAR1, EEAR0)
SFR_B_R(0x1D, EEDR)
SFR_B_N(0x1C, EECR, Dummy7, Dummy6, EEPM1, EEPM0, EERIE, EEMWE, EEWE, EERE)
SFR_B_N(0x18, PORTB, Dummy7, Dummy6, PORTB5, PORTB4, PORTB3, PORTB2, PORTB1, PORTB0)
SFR_B_N(0x17, DDRB, Dummy7, Dummy6, DDB5, DDB4, DDB3, DDB2, DDB1, DDB0)
SFR_B_N(0x16, PINB, Dummy7, Dummy6, PINB5, PINB4, PINB3, PINB2, PINB1, PINB0)
SFR_B_N(0x15, PCMSK, Dummy7, Dummy6, PCINT5, PCINT4, PCINT3, PCINT2, PCINT1, PCINT0)
SFR_B_N(0x14, DIDR0, Dummy7, Dummy6, ADC0D, ADC2D, ADC3D, ADC1D, AIN1D, AIN0D)
SFR_B_R(0x13, GPIOR2)
SFR_B_R(0x12, GPIOR1)
SFR_B_R(0x11, GPIOR0)
SFR_B_R(0x10, USIBR)
SFR_B_R(0x0F, USIDR)
SFR_B_N(0x0E, USISR, USISIF, USIOIF, USIPF, USIDC, USICNT3, USICNT2, USICNT1, USICNT0)
SFR_B_N(0x0D, USICR, USISIE, USIOIE, USIWM1, USIWM0, USICS1, USICS0, USICLK, USITC)
SFR_B_N(0x08, ACSR, ACD, ACBG, ACO, ACI, ACIE, Dummy2, ACIS1, ACIS0)
SFR_B_N(0x07, ADMUX, REFS1, REFS0, ADLAR, REFS2, MUX3, MUX2, MUX1, MUX0)
SFR_B_N(0x06, ADCSRA, ADEN, ADSC, ADATE, ADIF, ADIE, ADPS2, ADPS1, ADPS0)
SFR_W_R(0x04, ADC)
SFR_B_N(0x03, ADCSRB, BIN, ACME, IPR, Dummy4, Dummy3, ADTS2, ADTS1, ADTS0)
#ifndef __IOTINY85_H
#define __IOTINY85_H
/* SFRs are local in assembler modules (so this file may need to be */
/* included in more than one module in the same source file), */
/* but #defines must only be made once per source file. */
/*==============================*/
/* Interrupt Vector Definitions */
/*==============================*/
/* NB! vectors are specified as byte addresses */
#define RESET_vect (0x00) /* External Pin, Power-on Reset, Brown-out Reset,
Watchdog Reset */
#define INT0_vect (0x02) /* External Interrupt Request 0 */
#define PCINT0_vect (0x04) /* Pin Change Interrupt Request 0 */
#define TIM1_COMPA_vect (0x06) /* Timer/Counter1 Compare Match A */
#define TIM1_OVF_vect (0x08) /* Timer/Counter1 Overflow */
#define TIM0_OVF_vect (0x0A) /* Timer/Counter0 Overflow */
#define EE_RDY_vect (0x0C) /* EEPROM Ready */
#define ANA_COMP_vect (0x0E) /* Analog Comparator */
#define ADC_vect (0x10) /* ADC Conversion Complete */
#define TIM1_COMPB_vect (0x12) /* Timer/Counter1 Compare Match B */
#define TIM0_COMPA_vect (0x14) /* Timer/Counter0 Compare Match A */
#define TIM0_COMPB_vect (0x16) /* Timer/Counter0 Compare Match B */
#define WDT_vect (0x18) /* Watchdog Time-out */
#define USI_START_vect (0x1A) /* USI START */
#define USI_OVF_vect (0x1C) /* USI Overflow */
#ifdef __IAR_SYSTEMS_ASM__
#ifndef ENABLE_BIT_DEFINITIONS
#define ENABLE_BIT_DEFINITIONS
#endif /* ENABLE_BIT_DEFINITIONS */
#endif /* __IAR_SYSTEMS_ASM__ */
#ifdef ENABLE_BIT_DEFINITIONS
/* Bit definitions for use with the IAR Assembler
The Register Bit names are represented by their bit number (0-7).
*/
/* SP */
#define SP8 0
#define SP7 7
#define SP6 6
#define SP5 5
#define SP4 4
#define SP3 3
#define SP2 2
#define SP1 1
#define SP0 0
/* GIMSK */
#define INT0 6
#define PCIE 5
/* GIFR */
#define INTF0 6
#define PCIF 5
/* TIMSK */
#define OCIE1A 6
#define OCIE1B 5
#define OCIE0A 4
#define OCIE0B 3
#define TOIE1 2
#define TOIE0 1
/* TIFR */
#define OCF1A 6
#define OCF1B 5
#define OCF0A 4
#define OCF0B 3
#define TOV1 2
#define TOV0 1
/* SPMCSR */
#define CTPB 4
#define RFLB 3
#define PGWRT 2
#define PGERS 1
#define SPMEN 0
/* MCUCR */
#define PUD 6
#define SE 5
#define SM1 4
#define SM0 3
#define ISC01 1
#define ISC00 0
/* MCUSR */
#define WDRF 3
#define BORF 2
#define EXTRF 1
#define PORF 0
/* TCCR0B */
#define FOC0A 7
#define FOC0B 6
#define WGM02 3
#define CS02 2
#define CS01 1
#define CS00 0
/* TCCR1 */
#define CTC1 7
#define PWM1A 6
#define COM1A1 5
#define COM1A0 4
#define CS13 3
#define CS12 2
#define CS11 1
#define CS10 0
/* GTCCR */
#define TSM 7
#define PWM1B 6
#define COM1B1 5
#define COM1B0 4
#define FOC1B 3
#define FOC1A 2
#define PSR1 1
#define PSR0 0
/* TCCR0A */
#define COM0A1 7
#define COM0A0 6
#define COM0B1 5
#define COM0B0 4
#define WGM01 1
#define WGM00 0
/* PLLCSR */
#define SM 7
#define PCKE 2
#define PLLE 1
#define PLOCK 0
/* CLKPR */
#define CLKPCE 7
#define CLKPS3 3
#define CLKPS2 2
#define CLKPS1 1
#define CLKPS0 0
/* DT1A */
#define DT1AH3 7
#define DT1AH2 6
#define DT1AH1 5
#define DT1AH0 4
#define DT1AL3 3
#define DT1AL2 2
#define DT1AL1 1
#define DT1AL0 0
/* DT1B */
#define DT1BH3 7
#define DT1BH2 6
#define DT1BH1 5
#define DT1BH0 4
#define DT1BL3 3
#define DT1BL2 2
#define DT1BL1 1
#define DT1BL0 0
/* DTPS */
#define DTPS1 1
#define DTPS0 0
/* WDTCR */
#define WDTIF 7
#define WDTIE 6
#define WDP3 5
#define WDCE 4
#define WDE 3
#define WDP2 2
#define WDP1 1
#define WDP0 0
/* PRR */
#define PRTIM1 3
#define PRTIM0 2
#define PRUSI 1
#define PRADC 0
/* EEARH */
#define EEAR8 0
/* EEARL */
#define EEAR7 7
#define EEAR6 6
#define EEAR5 5
#define EEAR4 4
#define EEAR3 3
#define EEAR2 2
#define EEAR1 1
#define EEAR0 0
/* EECR */
#define EEPM1 5
#define EEPM0 4
#define EERIE 3
#define EEMWE 2
#define EEWE 1
#define EERE 0
/* PORTB */
#define PORTB5 5
#define PORTB4 4
#define PORTB3 3
#define PORTB2 2
#define PORTB1 1
#define PORTB0 0
/* PB */
#define PB5 5
#define PB4 4
#define PB3 3
#define PB2 2
#define PB1 1
#define PB0 0
/* DDRB */
#define DDB5 5
#define DDB4 4
#define DDB3 3
#define DDB2 2
#define DDB1 1
#define DDB0 0
/* PINB */
#define PINB5 5
#define PINB4 4
#define PINB3 3
#define PINB2 2
#define PINB1 1
#define PINB0 0
/* PCMSK */
#define PCINT5 5
#define PCINT4 4
#define PCINT3 3
#define PCINT2 2
#define PCINT1 1
#define PCINT0 0
/* DIDR0 */
#define ADC0D 5
#define ADC2D 4
#define ADC3D 3
#define ADC1D 2
#define AIN1D 1
#define AIN0D 0
/* USISR */
#define USISIF 7
#define USIOIF 6
#define USIPF 5
#define USIDC 4
#define USICNT3 3
#define USICNT2 2
#define USICNT1 1
#define USICNT0 0
/* USICR */
#define USISIE 7
#define USIOIE 6
#define USIWM1 5
#define USIWM0 4
#define USICS1 3
#define USICS0 2
#define USICLK 1
#define USITC 0
/* ACSR */
#define ACD 7
#define ACBG 6
#define ACO 5
#define ACI 4
#define ACIE 3
#define ACIS1 1
#define ACIS0 0
/* ADMUX */
#define REFS1 7
#define REFS0 6
#define ADLAR 5
#define REFS2 4
#define MUX3 3
#define MUX2 2
#define MUX1 1
#define MUX0 0
/* ADCSRA */
#define ADEN 7
#define ADSC 6
#define ADATE 5
#define ADIF 4
#define ADIE 3
#define ADPS2 2
#define ADPS1 1
#define ADPS0 0
/* ADCSRB */
#define BIN 7
#define ACME 6
#define IPR 5
#define ADTS2 2
#define ADTS1 1
#define ADTS0 0
/* Pointer definition */
#define XL r26
#define XH r27
#define YL r28
#define YH r29
#define ZL r30
#define ZH r31
/* Constants */
#define RAMEND 0x025F /*Last On-Chip SRAM location*/
#define XRAMEND 0x025F
#define E2END 0x01FF
#define FLASHEND 0x1FFF
#endif /* ENABLE_BIT_DEFINITIONS */
#endif /* __IOTINY85_H (define part) */
#endif /* __IOTINY85_H (SFR part) */
*************************************************************************
/* - lnktiny85s.xcl -
*
* XLINK command file for the ICCAVR C-compiler using the --cpu=tiny85, -ms
* options.
*
* Usage: xlink your_file(s) -f lnktiny85
*
* File version: $Revision: 1.3 $
*/
/*
* Modify the lines below to alter the size of the RSTACK, CSTACK and HEAP
* segments. These need to be fine tuned to suit your specific application.
* The '_..X_' prefix is used by C-SPY as an indication that the label should
* not be displayed in the dissassembly window.
*/
-D_..X_CSTACK_SIZE=20 /* 32 bytes for auto variables and saved registers. */
-D_..X_RSTACK_SIZE=10 /* 16 bytes for return addresses, equivalent to 8 */
/* levels of calls, including interrupts. */
-D_..X_HEAP_SIZE=10 /* 16 bytes of heap. */
-D_..X_NEAR_HEAP_SIZE=10 /* 16 bytes of heap. */
/* Define CPU */
-ca90
/*
* The following segments are located in the internal memory of
* the ATtiny85. Do not change these lines.
*/
/* Code memory */
-D_..X_INTVEC_SIZE=1E // 2 bytes * 15 vectors
-D_..X_FLASH_END=1FFF // End of flash memory
-Z(CODE)INTVEC=0-(_..X_INTVEC_SIZE-1)
/* Fill unused interrupt vector's with RETI */
-H1895 -h(CODE)0-_..X_INTVEC_SIZE
-Z(CODE)TINY_F=_..X_INTVEC_SIZE-FF
-Z(CODE)NEAR_F=_..X_INTVEC_SIZE-_..X_FLASH_END
-Z(CODE)SWITCH=_..X_INTVEC_SIZE-_..X_FLASH_END
-Z(CODE)INITTAB=_..X_INTVEC_SIZE-_..X_FLASH_END
-Z(CODE)DIFUNCT=_..X_INTVEC_SIZE-_..X_FLASH_END
-Z(CODE)CODE=_..X_INTVEC_SIZE-_..X_FLASH_END
-Z(CODE)TINY_ID=_..X_INTVEC_SIZE-_..X_FLASH_END
-Z(CODE)NEAR_ID=_..X_INTVEC_SIZE-_..X_FLASH_END
-Z(CODE)CHECKSUM#_..X_FLASH_END
/* Internal data memory */
-D_..X_SRAM_BASE=60
-D_..X_SRAM_TEND=FF
-D_..X_SRAM_END=25F
-Z(DATA)TINY_I,TINY_Z,TINY_N=_..X_SRAM_BASE-_..X_SRAM_TEND
-Z(DATA)CSTACK+_..X_CSTACK_SIZE=_..X_SRAM_BASE-_..X_SRAM_END
-Z(DATA)HEAP+_..X_HEAP_SIZE=_..X_SRAM_BASE-_..X_SRAM_END
-Z(DATA)IOSTREAM_N#_..X_SRAM_BASE-_..X_SRAM_END
-Z(DATA)NEAR_HEAP+_..X_NEAR_HEAP_SIZE=_..X_SRAM_BASE-_..X_SRAM_END
-Z(DATA)RSTACK+_..X_RSTACK_SIZE=_..X_SRAM_BASE-_..X_SRAM_END
-Z(DATA)NEAR_I,NEAR_Z=_..X_SRAM_BASE-_..X_SRAM_END
/* Internal eeprom memory */
-D_..X_EEPROM_END=1FF // End of eeprom memory
-D_..X_EEPROM_START=0
-Z(XDATA)EEPROM_I,EEPROM_N=_..X_EEPROM_START-_..X_EEPROM_END
/* Select reduced "printf" support to reduce library size.
See configuration section in manual concerning printf/sprintf. */
/*Dlib*/
-e_PrintfSmall=_Printf
/*Clib*/
-e_small_write=_formatted_write
-e_small_write_P=_formatted_write_P
/* Disable floating-point support in "scanf" to reduce library size.
See configuration section in manual concerning scanf/sscanf */
/*Dlib*/
-e_ScanfSmall=_Scanf
/*Clib*/
-e_medium_read=_formatted_read
-e_medium_read_P=_formatted_read_P
/* Suppress one warning which is not relevant for this processor */
-w29
/* Code will now reside in file aout.a90 or aout.d90, unless -o is specified */
/* .d90 is the default if debug system is linked (option -r) */
/* .a90 is the default without debugging. Default format is -Fmotorola */
