bestsave on $\best.w
status_file $\progress.sts

unit mil
grid wire 1.000000
grid via 5.000000

rule pcb (pin_width_taper down (max_length 80))
rule pcb (width 7) (clearance 7)
rule pcb (limit_vias 6)
rule pcb (clearance 8 (type smd_via))
rule pcb (clearance 8 (type pin_via))
rule pcb (via_at_smd off)

define (pair (nets BFS?+ BFS?- (gap 8)))
define (pair (nets BCLK?+ BCLK?- (gap 8)))
define (pair (nets BDX?+ BDX?- (gap 8)))
define (pair (nets BDR?+ BDR?- (gap 8)))

set average_pair_length on

rule class POWER (width 14.0) (clearance 9 (type wire_wire))
rule class CVDD (width 18.0) (clearance 10 (type wire_wire))
rule class DIFF0 (width 10.0) (clearance 10 ) (limit_vias 1)
rule class DIFF1 (width 10.0) (clearance 10 ) (limit_vias 1)
rule class CLOCKS (width 12) (clearance 10 (type wire_wire)) (limit_vias 4)
rule class PLL (width 10) (clearance 10 (type wire_wire)) (limit_vias 2)

circuit class POWER (use_via medium_via) (priority 150)
circuit class CVDD (use_via medium_via) (priority 150)
circuit class CLOCKS (use_via medium_via) (priority 150)
circuit class DIFF0 (use_via min_via) (priority 150) (match_net_length on (tolerance 101))
circuit class DIFF1 (use_via min_via) (priority 150) (match_net_length on (tolerance 101))
circuit class OTHER (use_via min_via)
circuit class PLL (use_via min_via) (priority 200)

direction TOP diagonal
direction INT1 orthogonal
direction INT2 orthogonal
direction BOTTOM diagonal

cost side_exit free
cost off_center free
cost layer Top free (type length)
cost layer Top free (type way)
cost layer Int1 free (type length)
cost layer Int1 forbidden (type way)
cost layer Int2 free (type length)
cost layer Int2 forbidden (type way)
cost layer Bottom free (type length)
cost layer Bottom free (type way)

protect all vias
protect all wires

via_at_smd off

select component U1
select component U2
select component U3
select component U4
select component U5
select component U6
select component U7
select component U8
select component U9
select component U10
fanout 1 (direction in_out) (max_len 350) (location anywhere) (pin_share on) (smd_share on) (via_share on) (share_len 305) (pin_type power)
unselect all objects

select component U3
select component U4
select component U5
select component U6
select component U7
fanout 1 (smart_via_grid one_wire_between) (direction in_out) (max_len 250) (location anywhere) (pin_share off) (smd_share off) (via_share off) (pin_type all)
unselect all objects

select component U1
select component U2
fanout 1 (direction in_out) (max_len 250) (location anywhere) (pin_share off) (smd_share off) (via_share off) (pin_type all)
unselect all objects

bus diagonal

set diagonal_mode always
set dynamic_pinswap on
#select all bundle
select all pair
cost via high
route 40
protect selected_wires
unselect all objects
tax way 4

cost via medium
route 3
cost via high
route 20
clean 2
tax way 8
tax via 4
route 25 10
clean 2
route 25 30
clean 4
route 1
route 30 65
clean 8


write wire $\packer_a.w
center
spread (extra 20 1)
miter (pin) (tjunction) (bend) (style diagonal)
critic
write wire $\packer_a.m

write session $\packer_a.ses
report status $\packer_a.sts