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􀂄ARM7TDMI-S processor, running at up to 72 MHz.
􀂄512 kB on-chip flash program memory with In-System Programming (ISP) and In-Application Programming (IAP) capabilities. Flash program memory is on the ARM local bus for high performance CPU access.
􀂄64 kB of SRAM on the ARM local bus for high performance CPU access.
􀂄16 kB SRAM for Ethernet interface. Can also be used as general purpose SRAM.
􀂄16 kB SRAM for general purpose DMA use also accessible by USB.
􀂄Dual Advanced High-performance Bus (AHB) system that provides for simultaneous Ethernet DMA, USB DMA, and program execution from on-chip flash with no contention between those functions. A bus bridge allows the Ethernet DMA to access the other AHB subsystem.
􀂄Advanced Vectored Interrupt Controller (VIC), supporting up to 32 vectored interrupts.
􀂄General Purpose AHB DMA controller (GPDMA) that can be used with the SSP serial interfaces, the I2S port, and the Secure Digital/MultiMediaCard (SD/MMC) card port, as well as for memory-to-memory transfers.
􀂄Serial interfaces:
􀂋Ethernet MAC with associated DMA controller. These functions reside on an independent AHB.
􀂋USB 2.0 full-speed device with on-chip PHY and associated DMA controller.
􀂋Four UARTs with fractional baud rate generation, one with modem control I/O, one with IrDA support, all with FIFO.
􀂋CAN controller with two channels.
􀂋SPI controller.
􀂋Two SSP controllers, with FIFO and multi-protocol capabilities. One is an alternate for the SPI port, sharing its interrupt and pins. These can be used with the GPDMA controller.
􀂋Three I2C-bus interfaces (one with open-drain and two with standard port pins).
􀂋I2S (Inter-IC Sound) interface for digital audio input or output. It can be used with the GPDMA.
􀂄Other peripherals:
􀂋SD/MMC memory card interface.
􀂋70 general purpose I/O pins with configurable pull-up/down resistors.
􀂋10-bit ADC with input multiplexing among 6 pins.
􀂋10-bit DAC.
􀂋Four general purpose timers/counters with a total of 8 capture inputs and 10 compare outputs. Each timer block has an external count input.
􀂋One PWM/timer block with support for three-phase motor control. The PWM has two external count inputs.
􀂋Real-Time Clock (RTC) with separate power pin, clock source can be the RTC oscillator or the APB clock.
􀂋2 kB SRAM powered from the RTC power pin, allowing data to be stored when the rest of the chip is powered off.
􀂋WatchDog Timer (WDT). The WDT can be clocked from the internal RC oscillator, the RTC oscillator, or the APB clock.
􀂄Standard ARM test/debug interface for compatibility with existing tools.
􀂄Emulation trace module supports real-time trace.
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