void uart0ISR(void)^
{^
uint8_t iid;^
unsigned cpsr;^
^
cpsr = enableIRQ();^
^
// loop until not more interrupt sources^
while (((iid = U0IIR) & UIIR_NO_INT) == 0)^
{^
// identify & process the highest priority interrupt^
switch (iid & UIIR_ID_MASK)^
{^
case UIIR_RLS_INT: // Receive Line Status^
U0LSR; // read LSR to clear^
break;^
^
#ifdef UART0_RX_INT_MODE^
case UIIR_CTI_INT: // Character Timeout Indicator^
case UIIR_RDA_INT: // Receive Data Available^
do^
{^
uint16_t temp;^
^
// calc next insert index & store character^
temp = (uart0_rx_insert_idx + 1) % UART0_RX_BUFFER_SIZE;^
uart0_rx_buffer[uart0_rx_insert_idx] = U0RBR;^
^
// check for more room in queue^
if (temp != uart0_rx_extract_idx)^
uart0_rx_insert_idx = temp; // update insert index^
}^
while (U0LSR & ULSR_RDR);^
^
break;^
#endif^
^
#ifdef UART0_TX_INT_MODE^
case UIIR_THRE_INT: // Transmit Holding Register Empty^
while (U0LSR & ULSR_THRE)^
{^
// check if more data to send^
^
if (uart0_tx_insert_idx != uart0_tx_extract_idx)^
{^
U0THR = uart0_tx_buffer[uart0_tx_extract_idx++];^
uart0_tx_extract_idx %= UART0_TX_BUFFER_SIZE;^
}^
else^
{^
// no^
uart0_tx_running = 0; // clear running flag^
break;^
}^
}^
^
break;^
#endif // UART0_TX_INT_MODE^
^
default: // Unknown^
U0LSR;^
U0RBR;^
break;^
}^
}^
//NI_D;^
restoreIRQ(cpsr);^
//VICVectAddr = 0x00000000; // clear this interrupt from the VIC^
//ISR_EXIT(); // recover registers and return^
}^
#ifdef UART0_TX_INT_MODE^
case UIIR_THRE_INT: // Transmit Holding Register Empty^
while (U0LSR & ULSR_THRE)^
{^
// check if more data to send^
^
if (uart0_tx_insert_idx != uart0_tx_extract_idx)^
{^
U0THR = uart0_tx_buffer[uart0_tx_extract_idx++];^
uart0_tx_extract_idx %= UART0_TX_BUFFER_SIZE;^
}^
else^
{^
// no^
uart0_tx_running = 0; // clear running flag^
break;^
}^
}^
^
break;^
#endif // UART0_TX_INT_MODE^
^
default: // Unknown^
U0LSR;^
U0RBR;^
break;^
}^
}^
//NI_D;^
restoreIRQ(cpsr);^
//VICVectAddr = 0x00000000; // clear this interrupt from the VIC^
//ISR_EXIT(); // recover registers and return^
}^