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1. The write/erase endurance specification applies to each FLASH bit, specifically to writing a '0' to that bit, followed by an erase operation which sets that bit back to a '1'. (A fully erased FLASH reads as all '1's).
2. Erasing a bit that is already a '1' does not constitute a write/erase cycle.
3. If you were to subject a FLASH page to several hundred thousand write/erase cycles, checking the page contents after each operation, the first failure you will see (actually, it's the only failure mode we've seen in millions of cycles of testing) is an 'erase' failure. That is, you erase the page and one of the bits in the page reads back as '0'. If you erase this page a second time, it is highly probable that this bit will read back as '1' following that erase.
4. The FLASH write and erase operations, regardless of their success or failure, do not impact the performance of the CPU. The CPU is stalled during these operations (peripherals remain active), and interrupts posted during this time are serviced in priority order after the FLASH operation has completed.
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