Отправлено BLACKEAGLE 20 марта 2002 г. 18:38 В ответ на: 1. ASM для Config Wizard отправлено BLACKEAGLE 20 марта 2002 г. 18:23

1TITLEWatchdog Timer Configuration
 2Select Timeout Interval
  3Timeout Interval: 1048576 x Tsysclk[FF=07,FF]D
  3Timeout Interval:  262144 x Tsysclk[FF=06,FF] 
  3Timeout Interval:   65636 x Tsysclk[FF=05,FF] 
  3Timeout Interval:   16384 x Tsysclk[FF=04,FF] 
  3Timeout Interval:    4096 x Tsysclk[FF=03,FF] 
  3Timeout Interval:    1024 x Tsysclk[FF=02,FF] 
  3Timeout Interval:     256 x Tsysclk[FF=01,FF] 
  3Timeout Interval:      64 x Tsysclk[FF=00,FF] 
 2WDT Controls 
  3Disable WDT[FF=00,00]{NX}@08
  3Disable WDT Lockout[FF=00,00]{NX}@64
  3Enable/Reset WDT[FF=00,00]{NX}@94
1Port I/0 Crossbar
 2External Data Memory Interface Configuration
  3EMIF Port Select
   4EMIF Active on P0-P3[A3=00,20]D@98
  3EMIF Multiplex Mode Select
   4EMIF Operates in Multiplexed address/data mode[A3=00,10]D@98
   4EMIF Operates in Non-Multiplexed mode(seperate address and data pins)[A3=10,10]@98
  3EMIF Operating Mode Select
   4Internal Only[A3=00,0C]D@BE
   4Split Mode without Bank Select[A3=04,0C]@BE
   4Split Mode with Bank Select[A3=08,0C]@BE
   4External Only[A3=0C,0C]@BE
  3ALE Pulse-Width Select Bits (only has effect in non-multiplexed mode)
   4ALE high and ALE low pulse width = 1 SYSCLK cycle[A3=00,03]D@BE
   4ALE high and ALE low pulse width = 2 SYSCLK cycle[A3=01,03]@BE
   4ALE high and ALE low pulse width = 3 SYSCLK cycle[A3=02,03]@BE
   4ALE high and ALE low pulse width = 4 SYSCLK cycle[A3=03,03]@BE
 2TITLEConfigure the XBRn Registers
  3Enable External Memory Interface Low-Port[E3=02,02]@9B
  3Select Peripherals to Enable
   4UART0 Enable[E1=04,04]{NX}@99
   4SPI0 Bus Enable[E1=02,02]{NX}@99
   4SMBus Enable[E1=01,01]{NX}@99
   4UART1 Enable[E3=04,04]{NX}@99
   4PCA
	5ECIE:PCA0 Counter Enable[E1=40,40]{NX}@99
    5PCA Modules
     6Enable CEX0,CEX1,CEX2,CEX3,CEX4[E1=28,38]@99
     6Enable CEX0,CEX1,CEX2,CEX3[E1=20,38]@99
     6Enable CEX0,CEX1,CEX2[E1=18,38]@99
     6Enable CEX0,CEX1[E1=10,38]@99
     6Enable CEX0[E1=08,38]@99
     6Disable Module I/O[E1=00,38]D@99
   4CP0 Enable[E1=80,80]{NX}@99
   4CP1 Enable[E2=01,01]{NX}@99
   4T0 Enable[E2=02,02]{NX}@99
   4/INT0 Enable[E2=04,04]{NX}@99
   4T1 Enable[E2=08,08]{NX}@99
   4/INT1 Enable[E2=10,10]{NX}@99 
   4T2 Enable[E2=20,20]{NX}@99
   4T2EX Enable[E2=40,40]{NX}@99
   4T4 Enable[E3=08,08]{NX}@99
   4T4EX Enable[E3=10,10]{NX}@99
   4SYSCLK Enable[E2=80,80]{NX}@99
   4CNVSTR Enable[E3=01,01]{NX}@99
   4Enable Crossbar[E3=40,40]{NX}
2TITLESelect Pin Mode
 3Port Pin Pull-Up Selection
  4Weak Pull-Ups globally disabled[E3=80,80]
 3Port Pin Output Mode
  4Port 0 Configure
   5Bit 0 of Port 0 Push Pull Output[A4=01,01]{NX}@67
   5Bit 1 of Port 0 Push Pull Output[A4=02,02]{NX}@67
   5Bit 2 of Port 0 Push Pull Output[A4=04,04]{NX}@67
   5Bit 3 of Port 0 Push Pull Output[A4=08,08]{NX}@67
   5Bit 4 of Port 0 Push Pull Output[A4=10,10]{NX}@67
   5Bit 5 of Port 0 Push Pull Output[A4=20,20]{NX}@67
   5Bit 6 of Port 0 Push Pull Output[A4=40,40]{NX}@67
   5Bit 7 of Port 0 Push Pull Output[A4=80,80]{NX}@67
  4Port 1 Configure
   5Bit 0 of Port 1 Push Pull Output[A5=01,01]{NX}@67
   5Bit 1 of Port 1 Push Pull Output[A5=02,02]{NX}@67
   5Bit 2 of Port 1 Push Pull Output[A5=04,04]{NX}@67
   5Bit 3 of Port 1 Push Pull Output[A5=08,08]{NX}@67
   5Bit 4 of Port 1 Push Pull Output[A5=10,10]{NX}@67
   5Bit 5 of Port 1 Push Pull Output[A5=20,20]{NX}@67
   5Bit 6 of Port 1 Push Pull Output[A5=40,40]{NX}@67
   5Bit 7 of Port 1 Push Pull Output[A5=80,80]{NX}@67
  4Port 2 Configure
   5Bit 0 of Port 2 Push Pull Output[A6=01,01]{NX}@67
   5Bit 1 of Port 2 Push Pull Output[A6=02,02]{NX}@67
   5Bit 2 of Port 2 Push Pull Output[A6=04,04]{NX}@67
   5Bit 3 of Port 2 Push Pull Output[A6=08, 08]{NX}@67
   5Bit 4 of Port 2 Push Pull Output[A6=10,10]{NX}@67
   5Bit 5 of Port 2 Push Pull Output[A6=20,20]{NX}@67
   5Bit 6 of Port 2 Push Pull Output[A6=40,40]{NX}@67
   5Bit 7 of Port 2 Push Pull Output[A6=80,80]{NX}@67
  4Port 3 Configure 
   5Bit 0 of Port 3 Push Pull Output[A7=01,01]{NX}@67
   5Bit 1 of Port 3 Push Pull Output[A7=02,02]{NX}@67
   5Bit 2 of Port 3 Push Pull Output[A7=04,04]{NX}@67
   5Bit 3 of Port 3 Push Pull Output[A7=08,08]{NX}@67
   5Bit 4 of Port 3 Push Pull Output[A7=10,10]{NX}@67
   5Bit 5 of Port 3 Push Pull Output[A7=20,20]{NX}@67
   5Bit 6 of Port 3 Push Pull Output[A7=40,40]{NX}@67
   5Bit 7 of Port 3 Push Pull Output[A7=80,80]{NX}@67
 3Port Pin Input Mode
  4Port 1
   5Bit 0 of Port 1 Analog[BD=00,01]{NX}@97
   5Bit 1 of Port 1 Analog[BD=00,02]{NX}@97
   5Bit 2 of Port 1 Analog[BD=00,04]{NX}@97
   5Bit 3 of Port 1 Analog[BD=00,08]{NX}@97
   5Bit 4 of Port 1 Analog[BD=00,10]{NX}@97
   5Bit 5 of Port 1 Analog[BD=00,20]{NX}@97
   5Bit 6 of Port 1 Analog[BD=00,40]{NX}@97
   5Bit 7 of Port 1 Analog[BD=00,80]{NX}@97
 2TITLEView port pinout
1TITLEComparators
 2Comparator 0
   3Enable Comparator 0 Output on the Port I/O Cross Bar?[E1=80,80]{NX}@99
   3Comparator 0 Initially Enabled? [9E=80,80]{NX}@16
   3Positive hysterisis?
    4Disabled [9E=00,0C]D@BE
	4'5mV'  [9E=04,0C]@BE
	4'10mV' [9E=08,0C]@BE
	4'20mV' [9E=0C,0C]@BE
   3Negative hysterisis?
    4Disabled [9E=00,03]D@BE
	4'5mV'  [9E=01,03]@BE
	4'10mV' [9E=02,03]@BE
	4'20mV' [9E=03,03]@BE
   3Comp0 Rising Edge Interrupt Enabled?[E6=20,20]{NX}@15
    4Comparator 0 Rising Edge Interrupt Priority High?[F6=20,20]@15
   3Comp0 Falling Edge Interrupt Enabled?[E6=10,10]{NX}@15
    4Comparator 0 Falling Edge Interrupt Priority High?[F6=10,10]@15
   3Enable Comparator 0 as Reset Source?[EF=20,20]{NX}@05
 2Comparator 1
  3Enable Comparator 1 Output on the Port I/O Cross Bar?[E2=01,01]{NX}@99
  3Comparator 1 Initially Enabled?[9F=80,80]{NX}@17
  3Positive hysterisis?
    4Disabled [9F=00,0C]D@BE
	4'5mV'  [9F=04,0C]@BE
	4'10mV' [9F=08,0C]@BE
	4'20mV' [9F=0C,0C]@BE
  3Negative hysterisis?
    4Disabled [9F=00,03]D@BE
	4'5mV'  [9F=01,03]@BE
	4'10mV' [9F=02,03]@BE
	4'20mV' [9F=03,03]@BE
  3Comp1 Rising Edge Interrupt Enabled?[E6=80,80]{NX}@15
   4Comparator 1 Rising Edge Interrupt Priority High?[F6=80,80]@15
  3Comp1 Falling Edge Interrupt Enabled?[E6=40,40]{NX}@15
   4Comparator 1 Falling Edge Interrupt Priority High?[F6=40,40]@15
1TITLEOscillator Configuration
 2Enable SYSCLK Output on the Port I/O Cross Bar?[E2=80,80]{NX}@99
 2Internal Oscillator
  3Enable Internal Oscillator?[B2=04,04]D{NX}@70
  3Select Internal Oscillator typical Frequency
   4'2MHz'[B2=00,03]D@0C 
   4'4MHz'[B2=01,03]@0D
   4'8MHz'[B2=02,03]@0E
   4'16MHz'[B2=03,03]@0F
 2External Oscillator
  3Select External Oscillator Mode to Enable
   4Off. XTAL1 pin is grounded internally[B1=00,60]@09
   4CMOS Clock on XTAL1 pin Note: XTAL1 is NOT 5V tolerant[B1=20,70]@09
   4CMOS Clock on XTAL1 pin with divide by 2 Stage Note: XTAL1 is NOT 5V tolerant[B1=30,70]D@09
   4RC Oscillator Mode with divide by 2 stage[B1=40,70]@09
    5Select Frequency
    5'f<=25KHz'[B1=00,07]D@68
    5'25KHz    5'50KHz    5'100KHz    5'200KHz    5'400KHz    5'800KHz    5'1.6MHz   4C Oscillator Mode with divide by 2 stage Note: frequency is inversely proportional with capacitance for C=100pF frequency is 1/3 of 33pFfor C=100pF frequency is 1/3 of 33pF[B1=40,70]@09
    5Select Frequency Assuming C=33pF and AV+=3.3V
    5'4.04KHz'[B1=00,07]D@69
    5'12.9KHz'[B1=01,07]@69
    5'40.40KHz'[B1=02,07]@69
    5'119KHz'[B1=03,07]@69
    5'349KHz'[B1=04,07]@69
    5'918KHz'[B1=05,07]@69
    5'3.86MHz'[B1=06,07]@69
    5'12.9MHz'[B1=07,07]@69
   4Crystal Oscillator Mode[B1=60,70]@09
    5Select Crystal Frequency
    5'f<=12.5kHz[B1=00,07]D@6A
    5'12.5kHz    5'30.35Hz    5'93.8kHz    5'267kHz    5'722kHz    5'2.23MHz    5'f>6.74MHz'[B1=07,07]@6A
   4Crystal Oscillator Mode with divide by 2 stage[B1=70,70]@09
    5Select Crystal Frequency
    5'f<=12.5kHz[B1=00,07]D@6B
    5'12.5kHz    5'30.35Hz    5'93.8kHz    5'267kHz    5'722kHz    5'2.23MHz    5'f>6.74MHz'[B1=07,07]@6B
 2Select CLK Source
  3Internal Oscillator?[B2=00,08]D@93
  3External Oscillator?[B2=08,08]@BE
  3Enable Missing Clock Detector?[B2=80,80]{NX}
1TITLEReference Control Register
 2Temperature Sensor Enabled?[D1=04,04]{NX}
 2Reference Buffer Control
  3Internal VREF[D1=01,01]@5E
 2ADC0 Reference Configuration
  3VREFA input[D1=00,10]D@BE
  3DAC0 output[D1=10,10]@BE
 2ADC1 Reference Configuration
  3VREFA input[D1=08,08]D@BE
  3AV+[D1=08,08]@BE 
 2Enable Internal Bias Generator?[D1=02,02]{NX}@B2
1TITLESPI Configuration
 2SPI Interrupt Enabled?[E6=01,01]{NX}@15
  3Set SPI Interrupt Priority High?[F6=01,01]@15
 2Enable SPI Bus I/O on the Port I/O Crossbar?[E1=02,02]{NX}@99
 2SPI Clock Phase
  3Data sampled on first edge of SCK?[9A=00,80]D@BE
  3Data sampled on second edge of SCK?[9A=80,80]@BE
 2SPI Clock Polarity
  3SCK data sampled on rising edge?[9A=00,40]D@BE
  3SCK data sampled on falling edge?[9A=40,40]@BE
 2SPI Frame Size
    3'1'[9A=00,07]@BE
    3'2'[9A=01,07]@BE
    3'3'[9A=02,07]@BE
    3'4'[9A=03,07]@BE
    3'5'[9A=04,07]@BE
    3'6'[9A=05,07]@BE
    3'7'[9A=06,07]@BE
    3'8'[9A=07,07]D@BE
  2SPI Clock Frequency
    3Frequency=SYSCLK/2[9A=00,00]@10	  
    3Frequency=SYSCLK/10[9A=00,00]@11
    3Frequency=SYSCLK/200[9A=00,00]@12
    3Click to Set Custom Frequency@13
 2Select Mode
  3Enable Master Mode?[F8=02,02]@6C
  3Enable Slave Mode?[F8=00,02]D@6C
 2Enable SPI?[F8=00,00]{NX}@14
1TITLEDAC Configuration
 2DAC0
  3Enable DAC0?[D4=80,80]{NX}@07
  3DAC0 Mode Bits
   4Output updates occur on a write to DAC0H[D4=00,18]D@BE
   4Output updates occur on Timer 3 overflow[D4=08,18]@BE
   4Output updates occur on Timer 4 overflow[D4=10,18]@BE
   4Output updates occur on Timer 2 overflow[D4=18,18]@BE
  3Data Format					     DAC0H	  DAC0L
   4Use DAC0H:DAC0L[11:0] (MSB=DAC0H.3)   0000 dddd	dddd dddd[D4=00,07]D@5F
   4Use DAC0H:DAC0L[12:1] (MSB=DAC0H.4)   000d dddd	dddd ddd0[D4=01,07]@5F
   4Use DAC0H:DAC0L[13:2] (MSB=DAC0H.5)   00dd dddd	dddd dd00[D4=02,07]@5F
   4Use DAC0H:DAC0L[14:3] (MSB=DAC0H.6)   0ddd dddd	dddd d000[D4=03,07]@5F
   4Use DAC0H:DAC0L[15:4] (MSB=DAC0H.7)   dddd dddd	dddd 0000[D4=04,07]@5F 
 2DAC1
  3Enable DAC1?[D7=80,80]{NX}@FE
  3DAC1 Mode Bits
   4Output updates occur on a write to DAC1H[D7=00,18]D@BE
   4Output updates occur on Timer 3 overflow[D7=08,18]@BE
   4Output updates occur on Timer 4 overflow[D7=10,18]@BE
   4Output updates occur on Timer 2 overflow[D7=18,18]@BE
  3Data Format					     DAC1H	  DAC1L
   4Use DAC1H:DAC1L[11:0] (MSB=DAC1H.3)   0000 dddd	dddd dddd[D7=00,07]D@60
   4Use DAC1H:DAC1L[12:1] (MSB=DAC1H.4)   000d dddd	dddd ddd0[D7=01,07]@60
   4Use DAC1H:DAC1L[13:2] (MSB=DAC1H.5)   00dd dddd	dddd dd00[D7=02,07]@60
   4Use DAC1H:DAC1L[14:3] (MSB=DAC1H.6)   0ddd dddd	dddd d000[D7=03,07]@60
   4Use DAC1H:DAC1L[15:4] (MSB=DAC1H.7)   dddd dddd	dddd 0000[D7=04,07]@60
1TITLEUART0 Configuration
 2UART Interrupt Configuration
  3Clear UART receive and Transmit Interrupt Flags(RECOMMENDED)?[98=00,00]{NX}@28 
  3Enable Serial Port (UART0) Interrupt?[A8=10,10]{NX}@29
   4Set Serial Port (UART0) Interrupt Priority High?[B8=10,10]@29
 2Enable UART0 I/O on the Port I/O Crossbar?[E1=04,04]{NX}@C0
 2Enable UART0 Receiver?[98=10,10]{NX}
 2Select UART0 Mode
  3 0: Synchronous Mode: Baud Rate=SYSCLK/12[98=00,C0]@6E
  3 1: Asynchronous Mode: 8-bit UART, Variable Baud Rate[98=40,C0]@6E
  3 2: Asynchronous Mode: 9-bit UART, Fixed Baud Rate[98=80,C0]@6E   
   4SYSCLK/32?[87=80,80]
   4SYSCLK/64?[87=00,80]D
  3 3: Asychronous Mode: 9-bit UART,Variable Baud Rate[98=C0,C0]@6E
 2Multiprocessor Communications (Modes 2 and 3 Only)
  3Enable Multiprocessor Communications[98=20,20]
  3Set Slave address mask/register@9A
 2Select Transmit Source (Modes 1 and 3 Only)
  3Use Timer 1 Tx Source?[88=40,40]@19
  3Use Timer 2 Tx Source?[C8=14,10]@27
 2Select Receive Source (Modes 1 and 3 Only)
  3Use Timer 1 Rx Source?[88=40,40]@19
  3Use Timer 2 Rx Source?[C8=24,20]@27
 2Configure Timer 1
  3SMOD0
   4Enable Serial Port Baud Rate Doubler(SMOD0=1)?[87=80,80]{NX}
  3Timer 1 uses system clock divided by 12(T1M0=0)[8E=00,10]{NX}@19
  3Timer 1 uses system clock(T1M0=1)[8E=10,10]@19
  3Click to set 8-bit TH1 reload value@18
 2Configure Timer 2
  3Click to set 16-bit RCAP2H:RCAP2L reload value@20
1TITLEUART1 Configuration
 2UART Interrupt Configuration
  3Clear UART receive and Transmit Interrupt Flags(RECOMMENDED)?[F1=00,00]{NX}@9D 
  3Enable Serial Port (UART1) Interrupt?[E7=40,40]{NX}@29
   4Set Serial Port (UART1) Interrupt Priority High?[F7=40,40]@29
 2Enable UART1 I/O on the Port I/O Crossbar?[E3=04,04]{NX}@C0
 2Enable UART1 Receiver?[F1=10,10]{NX}
 2Select UART1 Mode
  3 0: Synchronous Mode: Baud Rate=SYSCLK/12[F1=00,C0]@6E
  3 1: Asynchronous Mode: 8-bit UART, Variable Baud Rate[F1=40,C0]@6E
  3 2: Asynchronous Mode: 9-bit UART, Fixed Baud Rate[F1=80,C0]@6E
   4SYSCLK/32?[87=10,10]
   4SYSCLK/64?[87=00,10]D
  3 3: Asychronous Mode: 9-bit UART,Variable Baud Rate[F1=C0,C0]@6E
 2Multiprocessor Communications (Modes 2 and 3 only)
  3Enable Multiprocessor Communications[F1=20,20]
  3Set Slave address mask/register@9C
 2Select Transmit Source (Modes 1 and 3 only)
  3Use Timer 1 as Tx Source?[88=40,40]{NX}@C2
  3Use Timer 4 as Tx Source?[C9=14,10]{NX}@62
 2Select Receive Source (Modes 1 and 3 only)
  3Use Timer 1 as Rx Source?[88=40,40]{NX}@C2
  3Use Timer 4 as Rx Source?[C9=24,20]{NX}@62
 2Configure Timer 1
  3SMOD1
   4Enable Serial Port Baud Rate Doubler(SMOD1=1)?[87=10,10]{NX}
  3Timer 1 uses system clock divided by 12(T1M0=0)[8E=00,10]@19
  3Timer 1 uses system clock[8E=10,10]@19
  3Click to set 8-bit TH1 reload value@18
 2Configure Timer 4
  3Click to set 16-bit RCAP4H:RCAP4L reload value@B1
1TITLESMBus Configuration
 2Enable SMBus?[C0=40,40]
  3Enable Slave Mode?[C0=04,04]{NX}
   4Respond to General Call Address[C3=01,01]
   4Click to enter 7-bit Slave Address@2A
 2Enable SMBus Interrupt?[E6=02,02]{NX}@15
  3Set SMBus Interrupt Priority High?[F6=02,02]@15
 2SCL low timeout enabled?[C0=01,01]{NX}@BA
  3Configure Timer 3
   4Click to enter 16-bit Reload Value@58
   4Click to enter 16-bit Initial Value@59  
   4Timebase
    5SYSCLK/12[91=00,02]D@BB
   4Enable Timer 3?[91=04,04]{NX}
 2Enable SMBus Bus I/O on the Port I/O Crossbar?[E1=01,01]{NX}@99
 2SCL high timeout enabled?[C0=02,02]{NX}
 2Click to set SMBus Clock Rate (SMB0CR)@2B
1TITLEPCA Configuration
 2Enable PCA Module I/O on the Port I/O Crossbar?
  3Enable CEX0,CEX1,CEX2,CEX3,CEX4 on the Port I/O Crossbar[E1=28,38]@99
  3Enable CEX0,CEX1,CEX2,CEX3 on the Port I/O Crossbar[E1=20,38]@99
  3Enable CEX0,CEX1,CEX2 on the Port I/O Crossbar[E1=18,38]@99
  3Enable CEX0,CEX1 on the Port I/O Crossbar[E1=10,38]@99
  3Enable CEX0 on the Port I/O Crossbar[E1=08,38]@99
  3Disable Module I/O[E1=00,38]D@99
 2Enable PCA Interrupt?[E6=08,08]{NX}@15
  3Set PCA Interrupt Priority High?[F6=08,08]@15
 2Configure PCA counter
  3Timebase
   4SYSCLK/12[D9=00,0E]D@BE
   4SYSCLK/4[D9=02,0E]@BE
   4SYSCLK[D9=08,0E]@BE
   4Timer 0 overflow[D9=04,0E]@BE
   4High-to-low transitions on ECI(max rate = SYSCLK/4)[D9=06,0E]@BE
   4External Clock/8[D9=0A,0E]@BE
  3Start the PCA Counter/Timer?[D8=40,40]{NX}
  3Enable PCA Overflow interrupt?[D9=01,01]{NX}
  3Click to enter 16 bit counter value (PCA0L, PCA0H){NX}@BF
 2Enable PCA Counter Input on the Port I/O Crossbar?[E1=40,40]{NX}@99
 2Module 0
  3Module 0 Interrupt
   4Enable Module 0 interrupt ECCF[DA=01,01]{NX}@74
  3Capture Mode
   4Capture triggered by positive edge on CEXn[DA=20,FE]{NX}@74
   4Capture triggered by negative edge on CEXn[DA=10,FE]{NX}@74
  3Software Timer Mode click to enter 16-bit compare value[DA=48,FE]@30
  3High Speed Output Mode click to enter 16-bit compare value[DA=4C,FE]@30
  3 8-bit PWM[DA=42,FE]@35
  3 16-bit PWM[DA=C2,FE]@AC
  3Frequency Output Mode Set Module 0 Capture Compare Module high Byte[DA=46,FE]@B4
 2Module 1
  3Module 1 Interrupt
   4Enable Module 1 interrupt ECCF[DB=01,01]{NX}@79
  3Capture Mode
   4Capture triggered by positive edge on CEXn[DB=20,FE]{NX}@79
   4Capture triggered by negative edge on CEXn[DB=10,FE]{NX}@79
  3Software Timer Mode click to enter 16-bit compare value[DB=48,FE]@31
  3High Speed Output Mode click to enter 16-bit compare value[DB=4C,FE]@31
  3 8-bit PWM[DB=42,FE]@36
  3 16-bit PWM[DB=C2,FE]@AD
  3Frequency Output Mode Set Module 1 Capture Compare Module high Byte[DB=46,FE]@B5
 2Module 2  
  3Module 2 Interrupt
   4Enable Module 2 interrupt ECCF[DC=01,01]{NX}@7E
  3Capture Mode
   4Capture triggered by positive edge on CEXn[DC=20,FE]{NX}@7E
   4Capture triggered by negative edge on CEXn[DC=10,FE]{NX}@7E
  3Software Timer Mode click to enter 16-bit compare value[DC=48,FE]@32
  3High Speed Output Mode click to enter 16-bit compare value[DC=4C,FE]@32
  3 8-bit PWM[DC=42,FE]@37
  3 16-bit PWM[DC=C2,FE]@AE
  3Frequency Output Mode Set Module 2 Capture Compare Module high Byte[DC=46,FE]@B6
 2Module 3
  3Module 3 Interrupt
   4Enable Module 3 interrupt ECCF[DD=01,01]{NX}@83
  3Capture Mode
   4Capture triggered by positive edge on CEXn[DD=20,FE]{NX}@83
   4Capture triggered by negative edge on CEXn[DD=10,FE]{NX}@83
  3Software Timer Mode click to enter 16-bit compare value[DD=48,FE]@84
  3High Speed Output Mode click to enter 16-bit compare value[DD=4C,FE]@33
  3 8-bit PWM[DD=42,FE]@38
  3 16-bit PWM[DD=C2,FE]@AF
  3Frequency Output Mode Set Module 3 Capture Compare Module high Byte[DD=46,FE]@B7
 2Module 4
  3Module 4 Interrupt
   4Enable Module 4 interrupt ECCF[DE=01,01]{NX}@88
  3Capture Mode
   4Capture triggered by positive edge on CEXn[DE=20,FE]{NX}@88
   4Capture triggered by negative edge on CEXn[DE=10,FE]{NX}@88
  3Software Timer Mode click to enter 16-bit compare value[DE=48,FE]@34
  3High Speed Output Mode click to enter 16-bit compare value[DE=4C,FE]@34
  3 8-bit PWM[DE=42,FE]@39
  3 16-bit PWM[DE=C2,FE]@B0
  3Frequency Output Mode Set Module 4 Capture Compare Module high Byte[DE=46,FE]@B8
1TITLEADC0 Configuration
 2Enable ADC0?[E8=80,80]{NX}@B2
 2Start of Conversion Source
   3AD0BUSY[E8=00,0C]D@91
   3Timer 2 Overflow[E8=0C,0C]@91
   3Timer 3 Overflow[E8=04,0C]@91
   3External CNVSTR[E8=08,0C]@91
    4Enable CNVSTR on the Port I/O Crossbar?[E3=01,01]{NX}@99
  2ADC Data Justification
   3Right Justified 0x0ddd[E8=00,01]D@BE
   3Left Justified  0xddd0[E8=01,01]@BE
  2AMUX Configuration
   3Single Ended or Differential input Selector
    4AIN0 and AIN1
     5AIN0 and AIN1 are independent single-ended inputs[BA=00,01]D@8C
     5AIN0, AIN1 are (respectively) +,- differential input pair[BA=01,01]@8C
    4AIN2 and AIN3
     5AIN2 and AIN3 are independent single-ended inputs[BA=00,02]D@8D
     5AIN2, AIN3 are (respectively) +,- differential input pair[BA=02,02]@8D
    4AIN4 and AIN5
     5AIN4 and AIN5 are independent single-ended inputs[BA=00,04]D@8E
     5AIN4, AIN5 are (respectively) +,- differential input pair[BA=04,04]@8E
    4AIN6 and AIN7
     5AIN6 and AIN7 are independent single-ended inputs[BA=00,08]D@8F
     5AIN6, AIN7 are (respectively) +,- differential input pair[BA=08,08]@8F
   3Channel Selector
    4AIN0[BB=00,0F]D@BE
    4AIN1[BB=00,00]@4A
    4AIN2[BB=02,0F]@BE
    4AIN3[BB=00,00]@4B
    4AIN4[BB=04,0F]@BE
    4AIN5[BB=00,00]@4C
    4AIN6[BB=06,0F]@BE
    4AIN7[BB=00,00]@4D
    4Temp Sensor[BB=08,08]@BE
 2PGA Gain Selector 
  3PGA Gain = 1[BC=00,07]D@BE
  3PGA Gain = 2[BC=01,07]@BE
  3PGA Gain = 4[BC=02,07]@BE
  3PGA Gain = 8[BC=03,07]@BE
  3PGA Gain = 16[BC=04,07]@BE
  3PGA Gain = 0.5[BC=06,07]@BE
 2Window Compare Configuration   
  3Click to Enter "LESS THAN" Threshold@4F
  3Click to Enter "GREATER THAN" Threshold@50  
 2Enable ADC0 End of Conversion Interrupt?[E7=02,02]{NX}@15
  3Set ADC0 End of Conversion Interrupt Priority High?[F7=02,02]@15
 2Enable ADC0 Window Comparison Interrupt?[E6=04,04]{NX}@15
  3Set ADC0 Window Comparison Interrupt Priority High?[F6=04,04]{NX}@15
 2SAR Clock Configuration@BC
 2Low power tracking mode[E8=C0,CC]{NX}@5C
1TITLEADC1 Configuration
 2Enable ADC1?[AA=80,80]{NX}@B2
 2Start of Conversion Source
  3AD1BUSY[AA=00,0E]D@91
  3Timer 2 Overflow[AA=06,0E]@91
  3Timer 3 Overflow[AA=02,0E]@BE
  3External CNVSTR[AA=04,0E]@BE
  3AD0BUSY (synchronized with ADC0 software)[AA=0E,0E]
 2PGA Gain Selector@6F
  3PGA Gain = 0.5[AB=06,07]@BE
  3PGA Gain = 1[AB=00,07]D@BE
  3PGA Gain = 2[AB=01,07]@BE
  3PGA Gain = 4[AB=02,07]@BE
 2AMUX Configuration
  3Channel Selector
   4AIN 1.0 selected[AC=00,07]D@B3
   4AIN 1.1 selected[AC=01,07]@B3
   4AIN 1.2 selected[AC=02,07]@B3
   4AIN 1.3 selected[AC=03,07]@B3
   4AIN 1.4 selected[AC=04,07]@B3
   4AIN 1.5 selected[AC=05,07]@B3
   4AIN 1.6 selected[AC=06,07]@B3
   4AIN 1.7 selected[AC=07,07]@B3
 2Enable ADC1 End of Conversion Interrupt?[E7=08,08]{NX}@15
  3Set ADC1 End of Conversion Interrupt Priority High?[F7=08,08]@15
 2SAR Clock Configuration@BD
 2Low power tracking mode[AA=40,40]{NX}@5C
1TITLETimers Configuration
 2Timer 0 and Timer 1
  3Timer 0
   4Enable Timer 0 Interrupt?[A8=02,02]{NX}@15
    5Set Timer 0 Interrpt Priority High?[B8=02,02]@15
   4Select Mode
    5 13-bit Counter/Timer[89=00,03]D@BE
    5 16-bit Counter/Timer[89=01,03]@BE
    5 Two 8-bit Counter Timers[89=03,03]@BE
    5 8-bit auto-reload click to enter 8-bit reload value[89=02,03]@51
   4Gate Timer 0 with /INT0?[89=08,08]{NX}
    5Enable /INT0 on the Port I/O Crossbar?[E2=04,04]@99
   4Timer 0 Timebase
    5Timer 0 uses SYSCLK[8E=08,08]@BE
    5Timer 0 uses SYSCLK/12[8E=00,08]D@BE
    5External T0[89=04,04]@BE
     6Enable T0 on Port I/O Cross Bar?[E2=02,02]@99
   4Enable Timer 0?[88=10,10]{NX}
   4Click to Enter Timer 0 Inital Value@52
  3Timer 1@61
   4Enable Timer 1 Interrupt?[A8=08,08]{NX}@15
    5Set Timer 1 Interrpt Priority High?[B8=08,08]@15
   4Select Mode
    5Timer 1 13-bit Counter/Timer Mode[89=00,30]D@62
    5Timer 1 16-bit Counter/Timer Mode[89=10,30]@62
    5 8-bit auto-reload click to enter 8-bit reload value[89=20,30]@53
    5Timer 1 Inactive OFF[89=30,30]@62
   4Gate Timer 1 with INT1?[89=80,80]{NX}
    5Enable /INT1 on the Port I/O Crossbar?[E2=10,10]@99
   4Timer 1 Timebase
    5Timer 1 uses SYSCLK[8E=10,10]@62
    5Timer 1 uses SYSCLK/12[8E=00,10]D@62
    5External T1[89=40,40]@62
     6Enable T1 on Port I/O Cross Bar?[E2=08,08]@99
   4Enable Timer 1?[88=40,40]{NX}@62
   4Click to Enter Timer 1 Inital Value@54
 2Timer 2@61
  3Enable Timer 2 Interrupt?[A8=20,20]{NX}@15
   4Set Timer 2 Interrpt Priority High?[B8=20,20]@15
  3Select Mode
   4 16-bit Capture[C8=0D,3D]
    5Enable T2EX on Port I/O Cross Bar?[E2=40,40]@99
   4 16-bit Auto-Reload click to enter 16-bit reload value[C8=04,3D]@55
   4 Baud Rate Generator[C8=34,34]@56
    5Use Timer 2 for receive clock?[C8=20,20]{NX}@56
    5Use Timer 2 for transmit clock?[C8=10,10]{NX}@56
  3Timer 2 Timebase
   4Timer 2 uses SYSCLK[8E=20,20]
   4Timer 2 uses SYSCLK/2 (UART Mode)[8E=00,00]@C1
   4Timer 2 uses SYSCLK/12[8E=00,20]D
   4External T2[C8=02,02]
    5Enable T2 on Port I/O Cross Bar?[E2=20,20]@99
  3Click to Enter Timer 2 16-bit Initial Value@5A
 2Timer 3 16-bit Auto-Reload
  3Enable Timer 3 Interrupt?[E7=01,01]{NX}@15
   4Set Timer 3 Interrpt Priority High?[F7=01,01]@15
  3Timebase
   4SYSCLK[91=02,02]
   4SYSCLK/12[91=00,02]D
  3Click to enter 16-bit Reload Value@58
  3Click to enter 16-bit Initial Value@59
  3Enable Timer 3?[91=04,04]{NX}
 2Timer 4 16-bit
  3Enable Timer 4 Interrupt?[E7=04,04]{NX}@15
   4Set Timer 4 Interrpt Priority High?[F7=04,04]@15
  3Select Mode
   4 16-bit Capture[C9=02,02]
    5Enable T4EX on Port I/O Cross Bar?[E3=10,10]@99
   4 16-bit Auto-Reload click to enter 16-bit reload value[C9=00,01]@AB
   4 Baud Rate Generator[C8=34,34]@56
    5Use Timer 4 for receive clock?[C9=20,20]{NX}@9F
    5Use Timer 4 for transmit clock?[C9=10,10]{NX}@9F
  3Timer 4 Timebase
   4Timer 4 uses SYSCLK[8E=40,40]
   4Timer 4 uses SYSCLK/2 (UART Mode)[8E=00,00]
   4Timer 4 uses SYSCLK/12[8E=00,40]D
   4External T4[C9=08,08]
    5Enable T4 on Port I/O Cross Bar?[E3=08,08]@99
   4Click to Enter Timer 4 16-bit Initial Value@AA
1TITLEReset Source Configuration
 2Enable Comparator 0 as a Reset Source?[EF=20,20]{NX}@05
 2Enable external CNVSTR signal as Reset Source[EF=40,40]{NX}@06
 2Enable Missing Clock Detector?[B2=80,80]{NX}
1TITLEInterrupt Configuration
 2Enable External /INT0?[A8=01,01]{NX}
  3Set External /INT0 Priority to High?[B8=01,01]
 2Enable External /INT1?[A8=04,04]{NX}
  3Set External /INT1 Priority to High?[B8=04,04]
 2Enable External IE6?[E7=10,10]{NX}
  3Set External IE6 Priority to High?[F7=10,10]
 2Enable External IE7?[E7=20,20]{NX} 
  3Set External IE7 Priority to High?[F7=20,20]
 2Enable SPI Interrupt?[E6=01,01]{NX}@15
  3Set SPI Interrupt Priority to High?[F6=01,01]@15
 2Comparator 0 Rising Edge Interrupt Enabled?[E6=20,20]{NX}@15
  3Set Comparator 0 Rising Edge Interrupt Priority to High?[F6=20,20]@15
 2Comparator 0 Falling Edge Interrupt Enabled?[E6=10,10]{NX}@15
  3Set Comparator 0 Falling Edge Interrupt Priority to High?[F6=10,10]@15
 2Comparator 1 Rising Edge Interrupt Enabled?[E6=80,80]{NX}@15
  3Set Comparator 1 Rising Edge Interrupt Priority to High?[F6=80,80]@15
 2Comparator 1 Falling Edge Interrupt Enabled?[E6=40,40]{NX}@15
  3Set Comparator 1 Falling Edge Interrupt Priority to High?[F6=40,40]@15
 2Serial Port (UART0) Interrupt Enabled?[A8=10,10]{NX}@29
  3Set Serial Port (UART0) Interrupt Priority to High?[B8=10,10]@29
 2Serial Port (UART1) Interrupt Enabled?[E7=40,40]{NX}@29
  3Set Serial Port (UART1) Interrupt Priority to High?[F7=40,40]@29
 2SMBus Interrupt Enabled?[E6=02,02]{NX}@15
  3Set SMBus Interrupt Priority to High?[F6=02,02]@15
 2PCA Interrupt Enabled?[E6=08,08]{NX}@15
  3Set PCA Interrupt Priority to High?[F6=08,08]@15
 2Timer 0 Interrupt Enabled?[A8=02,02]{NX}@15
  3Set Timer 0 Interrpt Priority to High?[B8=02,02]@15
 2Timer 1 Interrupt Enabled?[A8=08,08]{NX}@15
  3Set Timer 1 Interrpt Priority to High?[B8=08,08]@15
 2Timer 2 Interrupt Enabled?[A8=20,20]{NX}@15
  3Set Timer 2 Interrpt Priority to High?[B8=20,20]@15
 2Timer 3 Interrupt Enabled?[E7=01,01]{NX}@15
  3Set Timer 3 Interrpt Priority to High?[F7=01,01]@15
 2Timer 4 Interrupt Enabled?[E7=04,04]@15
  3Set Timer 4 Interrupt Priority to High?[F7=04,04]@15
 2ADC0 End of Conversion Interrupt Enabled?[E7=02,02]{NX}@15
  3Set ADC0 End of Conversion Interrupt Priority to High?[F7=02,02]@15
 2ADC0 Window Comparison Interrupt Enabled?[E6=04,04]{NX}@15
  3Set ADC0 Window Comparison Interrupt Priority to High?[F6=04,04]@15
 2ADC1 End of Conversion Interrupt Enabled?[E7=08,08]{NX}@15
  3Set ADC1 End of Conversion Interrupt Priority to High?[F7=08,08]@15
 2External Clock Source Valid Interrupt Enabled?[E7=80,80]{NX}
  3Set External Clock Source Valid Interrupt Priority to High?[F7=80,80]
 2Enable Global Interrupts?[A8=80,80]{NX}
END