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Copyright (C) 2001 CYGNAL INTEGRATED PRODUCTS, INC.
All rights reserved.
FILE NAME : C8051F020.INC
TARGET MCUs : C8051F020, 'F021, 'F022, 'F023
DESCRIPTION : Register/bit definitions for the C8051F02x product family.REVISION 1.0
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REGISTER DEFINITIONS0 DATA 080H ; PORT 0
P DATA 081H ; STACK POINTER
PL DATA 082H ; DATA POINTER - LOW BYTE
PH DATA 083H ; DATA POINTER - HIGH BYTE
4 DATA 084H ; PORT 4
5 DATA 085H ; PORT 5
6 DATA 086H ; PORT 6
CON DATA 087H ; POWER CONTROL
CON DATA 088H ; TIMER CONTROL
MOD DATA 089H ; TIMER MODE
L0 DATA 08AH ; TIMER 0 - LOW BYTE
L1 DATA 08BH ; TIMER 1 - LOW BYTE
H0 DATA 08CH ; TIMER 0 - HIGH BYTE
H1 DATA 08DH ; TIMER 1 - HIGH BYTE
KCON DATA 08EH ; CLOCK CONTROL
SCTL DATA 08FH ; PROGRAM STORE R/W CONTROL
1 DATA 090H ; PORT 1
MR3CN DATA 091H ; TIMER 3 CONTROL
MR3RLL DATA 092H ; TIMER 3 RELOAD REGISTER - LOW BYTE
MR3RLH DATA 093H ; TIMER 3 RELOAD REGISTER - HIGH BYTE
MR3L DATA 094H ; TIMER 3 - LOW BYTE
MR3H DATA 095H ; TIMER 3 - HIGH BYTE
7 DATA 096H ; PORT 7
CON0 DATA 098H ; SERIAL PORT 0 CONTROL
BUF0 DATA 099H ; SERIAL PORT 0 BUFFER
PI0CFG DATA 09AH ; SERIAL PERIPHERAL INTERFACE 0 CONFIGURATION
PI0DAT DATA 09BH ; SERIAL PERIPHERAL INTERFACE 0 DATA
DC1 DATA 09CH ; ADC 1 DATA
PI0CKR DATA 09DH ; SERIAL PERIPHERAL INTERFACE 0 CLOCK RATE CONTROL
PT0CN DATA 09EH ; COMPARATOR 0 CONTROL
PT1CN DATA 09FH ; COMPARATOR 1 CONTROL
2 DATA 0A0H ; PORT 2
MI0TC DATA 0A1H ; EMIF TIMING CONTROL
MI0CF DATA 0A3H ; EXTERNAL MEMORY INTERFACE (EMIF) CONFIGURATION
0MDOUT DATA 0A4H ; PORT 0 OUTPUT MODE CONFIGURATION
1MDOUT DATA 0A5H ; PORT 1 OUTPUT
CONFIGURATION
2MDOUT DATA 0A6H ; PORT 2 OUTPUT MODE CONFIGURATION
3MDOUT DATA 0A7H ; PORT 3 OUTPUT MODE CONFIGURATION
E DATA 0A8H ; INTERRUPT ENABLE
ADDR0 DATA 0A9H ; SERIAL PORT 0 SLAVE ADDRESS
DC1CN DATA 0AAH ; ADC 1 CONTROL
DC1CF DATA 0ABH ; ADC 1 ANALOG MUX CONFIGURATION
MX1SL DATA 0ACH ; ADC 1 ANALOG MUX CHANNEL SELECT
3IF DATA 0ADH ; PORT 3 EXTERNAL INTERRUPT FLAGS
ADEN1 DATA 0AEH ; SERIAL PORT 1 SLAVE ADDRESS MASK
MI0CN DATA 0AFH ; EXTERNAL MEMORY INTERFACE CONTROL
3 DATA 0B0H ; PORT 3
SCXCN DATA 0B1H ; EXTERNAL OSCILLATOR CONTROL
SCICN DATA 0B2H ; INTERNAL OSCILLATOR CONTROL
74OUT DATA 0B5H ; PORTS 4 - 7 OUTPUT MODE
LSCL DATA 0B6H ; FLASH MEMORY TIMING PRESCALER
LACL DATA 0B7H ; FLASH ACESS LIMIT
P DATA 0B8H ; INTERRUPT PRIORITY
ADEN0 DATA 0B9H ; SERIAL PORT 0 SLAVE ADDRESS MASK
MX0CF DATA 0BAH ; ADC 0 MUX CONFIGURATION
MX0SL DATA 0BBH ; ADC 0 MUX CHANNEL SELECTION
DC0CF DATA 0BCH ; ADC 0 CONFIGURATION
1MDIN DATA 0BDH ; PORT 1 INPUT MODE
DC0L DATA 0BEH ; ADC 0 DATA - LOW BYTE
DC0H DATA 0BFH ; ADC 0 DATA - HIGH BYTE
MB0CN DATA 0C0H ; SMBUS 0 CONTROL
MB0STA DATA 0C1H ; SMBUS 0 STATUS
MB0DAT DATA 0C2H ; SMBUS 0 DATA
MB0ADR DATA 0C3H ; SMBUS 0 SLAVE ADDRESS
DC0GTL DATA 0C4H ; ADC 0 GREATER-THAN REGISTER - LOW BYTE
DC0GTH DATA 0C5H ; ADC 0 GREATER-THAN REGISTER - HIGH BYTE
DC0LTL DATA 0C6H ; ADC 0 LESS-THAN REGISTER - LOW BYTE
DC0LTH DATA 0C7H ; ADC 0 LESS-THAN REGISTER - HIGH BYTE
2CON DATA 0C8H ; TIMER 2 CONTROL
4CON DATA 0C9H ; TIMER 4 CONTROL
CAP2L DATA 0CAH ; TIMER 2 CAPTURE REGISTER - LOW BYTE
CAP2H DATA 0CBH ; TIMER 2 CAPTURE REGISTER - HIGH BYTE
L2 DATA 0CCH ; TIMER 2 - LOW BYTE
H2 DATA 0CDH ; TIMER 2 - HIGH BYTE
MB0CR DATA 0CFH ; SMBUS 0 CLOCK RATE
SW DATA 0D0H ; PROGRAM STATUS WORD
EF0CN DATA 0D1H ; VOLTAGE REFERENCE 0 CONTROL
AC0L DA
TA 0D2H ; DAC 0 REGISTER - LOW BYTE
AC0H DATA 0D3H ; DAC 0 REGISTER - HIGH BYTE
AC0CN DATA 0D4H ; DAC 0 CONTROL
AC1L DATA 0D5H ; DAC 1 REGISTER - LOW BYTE
AC1H DATA 0D6H ; DAC 1 REGISTER - HIGH BYTE
AC1CN DATA 0D7H ; DAC 1 CONTROL
CA0CN DATA 0D8H ; PCA 0 COUNTER CONTROL
CA0MD DATA 0D9H ; PCA 0 COUNTER MODE
CA0CPM0 DATA 0DAH ; CONTROL REGISTER FOR PCA 0 MODULE 0
CA0CPM1 DATA 0DBH ; CONTROL REGISTER FOR PCA 0 MODULE 1
CA0CPM2 DATA 0DCH ; CONTROL REGISTER FOR PCA 0 MODULE 2
CA0CPM3 DATA 0DDH ; CONTROL REGISTER FOR PCA 0 MODULE 3
CA0CPM4 DATA 0DEH ; CONTROL REGISTER FOR PCA 0 MODULE 4
CC DATA 0E0H ; ACCUMULATOR
BR0 DATA 0E1H ; DIGITAL CROSSBAR CONFIGURATION REGISTER 0
BR1 DATA 0E2H ; DIGITAL CROSSBAR CONFIGURATION REGISTER 1
BR2 DATA 0E3H ; DIGITAL CROSSBAR CONFIGURATION REGISTER 2
CAP4L DATA 0E4H ; TIMER 4 CAPTURE REGISTER - LOW BYTE
CAP4H DATA 0E5H ; TIMER 4 CAPTURE REGISTER - HIGH BYTE
IE1 DATA 0E6H ; EXTERNAL INTERRUPT ENABLE 1
IE2 DATA 0E7H ; EXTERNAL INTERRUPT ENABLE 2
DC0CN DATA 0E8H ; ADC 0 CONTROL
CA0L DATA 0E9H ; PCA 0 TIMER - LOW BYTE
CA0CPL0 DATA 0EAH ; CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 0 - LOW BYTE
CA0CPL1 DATA 0EBH ; CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 1 - LOW BYTE
CA0CPL2 DATA 0ECH ; CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 2 - LOW BYTE
CA0CPL3 DATA 0EDH ; CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 3 - LOW BYTE
CA0CPL4 DATA 0EEH ; CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 4 - LOW BYTE
STSRC DATA 0EFH ; RESET SOURCE
DATA 0F0H ; B REGISTER
CON1 DATA 0F1H ; SERIAL PORT 1 CONTROL
BUF1 DATA 0F2H ; SERAIL PORT 1 DATA
ADDR1 DATA 0F3H ; SERAIL PORT 1
L4 DATA 0F4H ; TIMER 4 DATA - LOW BYTE
H4 DATA 0F5H ; TIMER 4 DATA - HIGH BYTE
IP1 DATA 0F6H ; EXTERNAL INTERRUPT PRIORITY REGISTER 1
IP2 DATA 0F7H ; EXTERNAL INTERRUPT PRIORITY REGISTER 2
PI0CN DATA 0F8H ; SERIA
L PERIPHERAL INTERFACE 0 CONTROL
CA0H DATA 0F9H ; PCA 0 TIMER - HIGH BYTE
CA0CPH0 DATA 0FAH ; CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 0 - HIGH BYTE
CA0CPH1 DATA 0FBH ; CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 1 - HIGH BYTE
CA0CPH2 DATA 0FCH ; CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 2 - HIGH BYTE
CA0CPH3 DATA 0FDH ; CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 3 - HIGH BYTE
CA0CPH4 DATA 0FEH ; CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 4 - HIGH BYTE
DTCN DATA 0FFH ; WATCHDOG TIMER CONTROL------------------------------------------------------------------------------
BIT DEFINITIONSTCON 88H
T0 BIT TCON.0 ; EXT. INTERRUPT 0 TYPE
E0 BIT TCON.1 ; EXT. INTERRUPT 0 EDGE FLAG
T1 BIT TCON.2 ; EXT. INTERRUPT 1 TYPE
E1 BIT TCON.3 ; EXT. INTERRUPT 1 EDGE FLAG
R0 BIT TCON.4 ; TIMER 0 ON/OFF CONTROL
F0 BIT TCON.5 ; TIMER 0 OVERFLOW FLAG
R1 BIT TCON.6 ; TIMER 1 ON/OFF CONTROL
F1 BIT TCON.7 ; TIMER 1 OVERFLOW FLAGSCON0 98H
I BIT SCON0.0 ; RECEIVE INTERRUPT FLAG
I BIT SCON0.1 ; TRANSMIT INTERRUPT FLAG
B8 BIT SCON0.2 ; RECEIVE BIT 8
B8 BIT SCON0.3 ; TRANSMIT BIT 8
EN BIT SCON0.4 ; RECEIVE ENABLE
M2 BIT SCON0.5 ; MULTIPROCESSOR COMMUNICATION ENABLE
M1 BIT SCON0.6 ; SERIAL MODE CONTROL BIT 1
M0 BIT SCON0.7 ; SERIAL MODE CONTROL BIT 0IE A8H
X0 BIT IE.0 ; EXTERNAL INTERRUPT 0 ENABLE
T0 BIT IE.1 ; TIMER 0 INTERRUPT ENABLE
X1 BIT IE.2 ; EXTERNAL INTERRUPT 1 ENABLE
T1 BIT IE.3 ; TIMER 1 INTERRUPT ENABLE
S BIT IE.4 ; SERIAL PORT INTERRUPT ENABLE
T2 BIT IE.5 ; TIMER 2 INTERRUPT ENABLE
A BIT IE.7 ; GLOBAL INTERRUPT ENABLEIP B8H
X0 BIT IP.0 ; EXTERNAL INTERRUPT 0 PRIORITY
T0 BIT IP.1 ; TIMER 0 PRIORITY
X1 BIT IP.2 ; EXTERNAL INTERRUPT 1 PRIORITY
T1 BIT IP.3 ; TIMER 1 PRIORITY
S BIT IP.4 ; SERIAL PORT PRIORITY
T2 BIT IP.5 ;
TIMER 2 PRIORITYSMB0CN C0H
MBTOE BIT SMB0CN.0 ; SMBUS 0 TIMEOUT ENABLE
MBFTE BIT SMB0CN.1 ; SMBUS 0 FREE TIMER ENABLE
A BIT SMB0CN.2 ; SMBUS 0 ASSERT/ACKNOWLEDGE FLAG
I BIT SMB0CN.3 ; SMBUS 0 INTERRUPT PENDING FLAG
TO BIT SMB0CN.4 ; SMBUS 0 STOP FLAG
TA BIT SMB0CN.5 ; SMBUS 0 START FLAG
NSMB BIT SMB0CN.6 ; SMBUS 0 ENABLET2CON C8H
PRL2 BIT T2CON.0 ; CAPTURE OR RELOAD SELECT
T2 BIT T2CON.1 ; TIMER OR COUNTER SELECT
R2 BIT T2CON.2 ; TIMER 2 ON/OFF CONTROL
XEN2 BIT T2CON.3 ; TIMER 2 EXTERNAL ENABLE FLAG
CLK BIT T2CON.4 ; TRANSMIT CLOCK FLAG
CLK BIT T2CON.5 ; RECEIVE CLOCK FLAG
XF2 BIT T2CON.6 ; EXTERNAL FLAG
F2 BIT T2CON.7 ; TIMER 2 OVERFLOW FLAGPSW D0H
BIT PSW.0 ; ACCUMULATOR PARITY FLAG
1 BIT PSW.1 ; USER FLAG 1
V BIT PSW.2 ; OVERFLOW FLAG
S0 BIT PSW.3 ; REGISTER BANK SELECT 0
S1 BIT PSW.4 ; REGISTER BANK SELECT 1
0 BIT PSW.5 ; USER FLAG 0
C BIT PSW.6 ; AUXILIARY CARRY FLAG
Y BIT PSW.7 ; CARRY FLAGPCA0CN D8H
CF0 BIT PCA0CN.0 ; PCA 0 MODULE 0 INTERRUPT FLAG
CF1 BIT PCA0CN.1 ; PCA 0 MODULE 1 INTERRUPT FLAG
CF2 BIT PCA0CN.2 ; PCA 0 MODULE 2 INTERRUPT FLAG
CF3 BIT PCA0CN.3 ; PCA 0 MODULE 3 INTERRUPT FLAG
CF4 BIT PCA0CN.4 ; PCA 0 MODULE 4 INTERRUPT FLAG
R BIT PCA0CN.6 ; PCA 0 COUNTER RUN CONTROL BIT
F BIT PCA0CN.7 ; PCA 0 COUNTER OVERFLOW FLAGADC0CN E8H
D0LJST BIT ADC0CN.0 ; ADC 0 RIGHT JUSTIFY DATA BIT
D0WINT BIT ADC0CN.1 ; ADC 0 WINDOW COMPARE INTERRUPT FLAG
D0STM0 BIT ADC0CN.2 ; ADC 0 START OF CONVERSION MODE BIT 0
D0STM1 BIT ADC0CN.3 ; ADC 0 START OF CONVERSION MODE BIT 1
D0BUSY BIT ADC0CN.4 ; ADC 0 BUSY FLAG
D0INT BIT ADC0CN.5 ; ADC 0 CONVERISION COMPLETE INTERRUPT FLAG
D0TM BIT ADC0CN.6 ; ADC 0 TRACK MODE
D0EN BIT ADC0CN.7 ; ADC 0 ENABLESPI0CN F8H
PIEN BIT SPI0CN.0 ; SPI 0 SPI ENABLE
STEN BIT SPI0C
N.1 ; SPI 0 MASTER ENABLE
LVSEL BIT SPI0CN.2 ; SPI 0 SLAVE SELECT
XBSY BIT SPI0CN.3 ; SPI 0 TX BUSY FLAG
XOVRN BIT SPI0CN.4 ; SPI 0 RX OVERRUN FLAG
ODF BIT SPI0CN.5 ; SPI 0 MODE FAULT FLAG
COL BIT SPI0CN.6 ; SPI 0 WRITE COLLISION FLAG
PIF BIT SPI0CN.7 ; SPI 0 INTERRUPT FLAG
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