Отправлено Точка опоры 26 декабря 2001 г. 12:22 В ответ на: Ответ: немного не то отправлено KWS 26 декабря 2001 г. 09:56

В "Errata" ( 01.99 ) есть пункт:

A skip instruction (SBRS, SBRC, SBIS, SBIC, CPSE) that skips a two-word instruction needs three clock cycles. If an interrupt occurs during the first or second clock cycle of this skip-instruction, the return address will not be stored correctly on the stack. In this situation, the address of the second word in the two-word instruction is stored. This means that on return from interrupt, the second word of the two-word command will be decoded and executed as an instruction.
The AT90S4414 has two two-word instructions: LDS and STS.
*** Типа, ошиблись в "Errate"... :-)
Note: This can only occur if all of the following conditions are true:
- A skip instruction is followed by a two-word instruction.
- The skip instruction is actually skipping the two-word instruction.
- Interrupts are enabled, and at least one interrupt source can generate an interrupt.
- An interrupt arrives in the first or second cycle of the skip instruction.
Note 2: This will only cause problems if the address of the following LDS or STS command points to an address beyond 400 Hex.

В последней редакции ( 09.01 ) эта фича по прежнему описана и добавлены фичи насчёт LDS/STS с последующим NOP. В результате портится R0.

• Увы, ни одной команды STS или LDS IAR не сгенерировал :(( — KWS   (26.12.2001 14:43, пустое)