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;Periphery setup:ldi temp,(1<
out TCCR1B,temp ;clear on compare match, CK/1 ldi temp,(1<
out TCCR1A,temp ;OC1A clear on compare ldi temp,high(FCLK/FUPD-1)
out OCR1AH,temp
ldi temp, low(FCLK/FUPD-1)
out OCR1AL,templdi temp,(1<
out TIFR,temp ;clear pending timer interrupt
out TIMSK,temp ;enable output compare interruptldi temp,(1<
out SPCR,temp ;SPI enable, MSB first, master ldi temp,(1<
out SPSR,temp ;double SPI speed ;собственно загрузка ЦАП:
ldi XL,(1<
out TCCR1A,XL ;OC1A toggle
ldi XL,(1<out TCCR1A,XL ;set SCK (OC1A force toggle)
Port_I2SWS_0 ;clear WS
out TCCR1A,XL ;clear SCK (OC1A force toggle)
out SPDR,SinH ;---> load DAC high byte
;здесь делаем что надо и
;ждем окончания передачи
out SPDR,SinL ;---> load DAC low byte
;опять кусок свободного времени :)
ldi XL,(1<out TCCR1A,XL ;OC1A force toggle
out SPDR,r0 ;zero data for another DAC channel
Port_I2SWS_1 ;set WS
ldi XL,(1<out TCCR1A,XL ;OC1A clear on compare