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|
//приемник (без бита паритета)
module rxd_232
(
input ti_20, ///// 20mhz // 115200
input rxd,
output reg [7:0] rg_rs232_out,
output reg frame_error,
output reg int_rs232_cpu
);
reg [1:0] dff_meta_rx;
reg [7:0] ct_period;
reg [3:0] ct_bit;
reg dff_enable_work;
reg stop;
reg [8:0] rg_rs232;
wire clr_enable_work;
always @ (posedge ti_20)
begin
dff_meta_rx <= {dff_meta_rx[0], rxd};
if (dff_meta_rx[1] & ~dff_enable_work) ct_period <= 8'h00;
else if (ct_period == 8'd173) ct_period <= 8'h00;
else ct_period <= ct_period + 1'b1;
if (dff_enable_work == 1'b0) ct_bit <= 4'h0;
else if ((ct_period == 8'd87) & (ct_bit != 4'h8)) ct_bit <= ct_bit + 1'b1;
end
assign clr_enable_work = stop | (dff_meta_rx[1] & ~dff_enable_work);
always @ (posedge ti_20, posedge clr_enable_work)
begin
if (clr_enable_work) dff_enable_work <= 1'b0;
else if (ct_period == 8'd87) dff_enable_work <= 1'b1;
end
always @ (posedge ti_20)
begin
if ((ct_period == 8'd87) & dff_enable_work) rg_rs232[ct_bit] <= dff_meta_rx[1];
stop <= (ct_period == 8'd87) & (ct_bit == 4'h8);
int_rs232_cpu <= stop;
if (stop) begin
rg_rs232_out <= rg_rs232[7:0];
frame_error <= ~rg_rs232[8]; end
end
endmodule