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2.3.3 Update Main Memory (SLE 4432 and SLE 4442)
The command programs the addressed EEPROM byte with the data byte transmitted. Depending
on the old and new data, one of the following sequences will take place during the processing mode:
– erase and write (5 ms) corresponding to m = 255 clock pulses
– write without erase (2.5 ms) corresponding to m = 124 clock pulses
– erase without write (2.5 ms) corresponding to m = 124 clock pulses
ВОТ ОНО
Additionally to the above functions the SLE 4442 provides a security code logic which controls the
write/erase access to the memory. For this purpose the SLE 4442 contains a 4-byte security
memory with an Error Counter EC (bit 0 to bit 2) and 3 bytes reference data. These 3 bytes as a
whole are called Programmable Security Code (PSC). After power on the whole memory, except for
the reference data, can only be read. Only after a successful comparison of verification data with the
internal reference data the memory has the identical access functionality of the SLE 4432 until the
power is switched off. After three successive unsuccessful comparisons the Error Counter blocks
any subsequent attempt, and hence any possibility to write and erase.
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