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CHGSTATUS Register (Address: 01h—Default Value: 00h)
TPS65010
SLVS149B–JUNE 2003–REVISED JANUARY 2005
CHGSTATUS B7 B6 B5 B4 B3 B2 B1 B0
Name USB charge AC charge Thermal Term Current Taper Chg Timeout Prechg BattTemp
Suspend Timeout Timeout error
Default 0 0 0 0 0 0 0 0
Read/write R R R R R/W R/W R/W R
The CHGSTATUS register contents indicate the status of charge.
Bit 7 - USB charge:
· 0 = inactive.
· 1 = USB source is present and in the range valid for charging. B7 remains active as long as the charge
source is present.
Bit 6 - AC charge:
· 0 = wall plug source is not present and/or not in the range valid for charging.
· 1 = wall plug source is present and in the range valid for charging. B6 remains active as long as the charge
source is present.
Bit 5 - Thermal suspend:
· 0 = charging is allowed
· 1 = charging is momentarily suspended due to excessive power dissipation on chip.
Bit 4 - Term current:
· 0 = charging, charge termination current threshold has not been crossed.
· 1 = charge termination current threshold has been crossed and charging has been stopped. It can be due to
a battery reaching full capacity, or it can be due to a battery removal condition.
Bit 3 - 1 Prechg Timeout, Chg Timeout, Taper Timeout:
· 0 = charging
· 1 = one of the timers has timed out and charging has been terminated.
Bit 0 - BattTemp error: Battery temperature error
· 0 = battery temperature is inside the allowed range and that charging is allowed.
· 1 = battery temperature is outside of the allowed range and that charging is suspended.
B1-4 may be reset via the serial interface in order to force a reset of the charger. Any attempt to write to B0 and
B5-7 is ignored. A 1 in B<7:0> sets the INT pin active unless the corresponding bit in the MASK register is set.
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REGSTATUS Register (Address: 02h—Default Value: 00h)
MASK1 Register (Address: 03h—Default Value: FFh)
TPS65010
SLVS149B–JUNE 2003–REVISED JANUARY 2005
REGSTATUS B7 B6 B5 B4 B3 B2 B1 B0
Bit name PB_ONOFF BATT_COVER UVLO PLGDOOO2D PLGDOOO1D PMGOAIOND PCGOOROED
Default 0 0 0 0 0 0 0 0
Read/write R R R R R R R R
Bit 7 - PB_ONOFF:
· 0 = inactive
· 1 = user activated the PB_ONOFF switch to request that all rails are shut down.
Bit 6 - BATT_COVER:
· 0 = BATT_COVER pin is high.
· 1 = BATT_COVER pin is low.
Bit 5 - UVLO:
· 0 = voltage at the VCC pin above UVLO threshold.
· 1 = voltage at the VCC pin has dropped below the UVLO threshold.
Bit 4 - not implemented
Bit 3 - PGOOD LDO2:
· 0 = LDO2 output in regulation, or LDO2 disabled with VREGS1<7> = 0
· 1 = LDO2 output out of regulation.
Bit 2 - PGOOD LDO1:
· 0 = LDO1 output in regulation, or LDO1 disabled with VREGS1<3> =0
· 1 = LDO1 output out of regulation.
Bit 1 - PGOOD MAIN:
· 0 = Main converter output in regulation.
· 1 = Main converter output out of regulation.
Bit 0 - PGOOD CORE:
· 0 = Core converter output in regulation.
· 1 = Core converter output out of regulation, or VDCDC2<7> = 1 in low power mode.
A rising edge in the REGSTATUS register contents causes INT to be driven low if it is not masked in the MASK2.
MASK1 B7 B6 B5 B4 B3 B2 B1 B0
Bit name Mask USB Mask AC MaSsuksTpheenrdmal Mask Term Mask Taper Mask Chg Mask Prechg BaMttTasekmp
Default 1 1 1 1 1 1 1 1
Read/write R/W R/W R/W R/W R/W R/W R/W R/W
The MASK1 register is used to mask all or any of the conditions in the corresponding CHGSTATUS<7:0>
positions being indicated at the INT pin. Default is to mask all.
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MASK2 Register (Address: 04h—Default Value: FFh)
ACKINT1 Register (Address: 05h—Default Value: 00h)
ACKINT2 Register (Address: 06h—Default Value: 00h)
CHGCONFIG Register Address: 07h—Default Value: 1Bh
TPS65010
SLVS149B–JUNE 2003–REVISED JANUARY 2005
MASK2 B7 B6 B5 B4 B3 B2 B1 B0
Bit name PB_MOaNskOFF BATTM_aCsOkVER Mask UVLO MaskLDPOG2OOD MaskLDPOG1OOD MaskMPAGINOOD Mask PGOOD CORE
Default 1 1 1 1 1 1 1
Read/write R/W R/W R/W R/W R/W R/W R/W R/W
The MASK2 register is used to mask all or any of the conditions in the corresponding REGSTATUS<7:0>
positions being indicated at the INT pin. Default is to mask all.
ACKINT1 B7 B6 B5 B4 B3 B2 B1 B0
Bit name Ack USB Ack AC ASckhuTthdeorwmnal Ack Term Ack Taper Ack Chg Ack Prechg BatAtTcekmp
Default 0 0 0 0 0 0 0 0
Read/write R R R R R R R R
The ACKINT1 register is internally used to acknowledge any of the interrupts in the corresponding
CHGSTATUS<7:0> positions. When this is done, the acknowledged interrupt is no longer fed through to the INT
pin and so the INT pin becomes free to indicate the next pending interrupt. If none exists, then the INT pin goes
high, else it will remain low. A 1 at any position in ACKINT1 is automatically cleared when the corresponding
interrupt condition in CHGSTATUS is removed. The application processor should not normally need to access
the ACKINT1 register.
ACKINT2 B7 B6 B5 B4 B3 B2 B1 B0
Bit name & function PB_AOcNkOFF AcCkOBVAETRT_ Ack UVLO AckLPDGOO2OD AckLPDGOO1OD AckMPAGINOOD AckCPOGROEOD
Default 0 0 0 0 0 0 0 0
Read/write R R R R R R R R
The ACKINT2 register is internally used to acknowledge any of the interrupts in the corresponding
REGSTATUS<7:0> positions. When this is done, the acknowledged interrupt is no longer fed through to the INT
pin and so the INT pin becomes free to indicate the next pending interrupt. If none exists, then the INT pin goes
high, else it will remain low. A 1 at any position in ACKINT2 is automatically cleared when the corresponding
interrupt condition in REGSTATUS is removed. The application processor should not normally need to access
the ACKINT2 register.
CHGCONFIG B7 B6 B5 B4 B3 B2 B1 B0
Bit name POR Charger reset ttiFimmaeesrtrec+nhtaaabrpgleeedr MScBurcrehnatrge LScBurcrheanrtge mUASB50/01m00A USaBllocwheadrge Cenhaabrglee
Default 0 0 0 1 1 0 1 1
Read/write R/W R/W R/W R/W R/W R/W R/W R/W
The CHGCONFIG register is used to configure the charger.
Bit 7 - POR:
· 0 = Tn(RESPWRON) duration typically 1000 ms (+/-25%)
· 1 = Tn(RESPWRON) duration typically 69 ms (+/-25%)
Bit 6 - Charger reset:
· Clears all the timers in the charger and forces a restart of the charge algorithm.
· 0 / 1 = This bit must be set and then reset via the serial interface.
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LED1_ON Register (Address: 08h—Default Value: 00h)
LED1_PER Register (Address: 09h—Default Value: 00h)
TPS65010
SLVS149B–JUNE 2003–REVISED JANUARY 2005
Bit 5 - Fast charge timer + taper timer enabled:
· 0 = fast charge timer disabled (default)
· 1 = enables the fast charge timer.
Bit 4, Bit 3 - MSB/LSB Charge current:
· Used to set the constant current in the current regulation phase.
B4:B3 CHARGE CURRENT RATE
11 Maximum current set by the external resistor at the ISET pin
10 75% of maximun
01 50% of maximun
00 25% of maximun
Bit 2 - USB 100 mA / 500 mA:
· 0 = sets the USB charging current to max 100 mA.
· 1 = sets the USB charging current to max 500mA. B2 is ignored if B1=0.
Bit 1 - USB charge allowed:
· 0 = prevents any charging from the USB input.
· 1 = charging from the USB input is allowed.
Bit 0 - Charge enable:
· 0 = charging is not allowed.
· 1 = charger is free to charge from either of the two input sources. If both sources are present and valid, the
TPS65010 charges from the ac source.
LED1_ON B7 B6 B5 B4 B3 B2 B1 B0
Bit name PG1 LED1 ON6 LED1 ON5 LED1 ON4 LED1 ON3 LED1 ON2 LED1 ON1 LED1 ON 0
Default 0 0 0 0 0 0 0 0
Read/write R/W R/W R/W R/W R/W R/W R/W R/W
The LED1_ON and LED1_PER registers can be used to take control of the PG open drain output normally
controlled by the charger.
Bit 7 - PG1: Control of the PG pin is determined by PG1 and PG2 according to the table under LED1_PER
register
Bit 6 - BIT 0 - LED1_ON<6:0> are used to program the on-time of the open drain output transistor at the PG pin.
The minimum on time is typically 10 ms and one LSB corresponds to a 10-ms step change in the on time.
LED1_PER B7 B6 B5 B4 B3 B2 B1 B0
Bit name PG2 LED1 PER6 LED1 PER5 LED1 PER4 LED1 PER3 LED1 PER2 LED1 PER1 LED1 PER 0
Default 0 0 0 0 0 0 0 0
Read/write R/W R/W R/W R/W R/W R/W R/W R/W
Bit 7 - PG2: Control of the PG pin is determined by PG1 and PG2 according to the following table. Default shown
in bold.
PG1 PG2 BEHAVIOR OF PG OPEN DRAIN OUTPUT
0 0 Under charger control
0 1 Blink
1 0 Off
1 1 Always On
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