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8.3 Use of the clock synchronizing mechanism as
a handshake
In addition to being used during the arbitration procedure, the clock synchronization mechanism can be used to enable receivers to cope with fast data transfers, on either a byte level or a bit level.
On the byte level, a device may be able to receive bytes of data at a fast rate, but needs more time to store a received byte or prepare another byte to be transmitted. Slaves can then hold the SCL line LOW after reception and acknowledgment of a byte to force the master into a wait state until the slave is ready for the next byte transfer in a
type of handshake procedure (see Fig.6).
On the bit level, a device such as a microcontroller with or without limited hardware for the I2C-bus, can slow down the bus clock by extending each clock LOW period. The speed of any master is thereby adapted to the internal operating rate of this device.
In Hs-mode, this handshake feature can only be used on byte level (see Section 13).
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