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## SM DO.file
bestsave on $\best.wstatus_file $\progress.stsunit milgrid wire 1.000000 grid via 5.000000 rule pcb (pin_width_taper down (max_length 80))rule pcb (width 7) (clearance 7)rule pcb (limit_vias 6)rule pcb (clearance 8 (type smd_via))rule pcb (clearance 8 (type pin_via))rule pcb (via_at_smd off)#define (bundle HPI_D (gap 7 (layer TOP BOTTOM INT1 INT2)) (nets HD0 HD1 HD2 HD3))#define (bundle HPI_D (add_net HD4 HD5 HD6 HD7 HD8 HD9 HD10 HD11 HD12 HD13 HD14 HD15))#define (bundle XED_L (gap 7 (layer TOP BOTTOM INT1 INT2)) (nets XED0 XED1 XED2 XED3))#define (bundle XED_L (add_net XED4 XED5 XED6 XED7 XED8 XED9 XED10 XED11))#define (bundle XED_L (add_net XED12 XED13 XED14 XED15))#define (bundle XED_H (gap 7 (layer TOP BOTTOM INT1 INT2)) (nets XED16 XED17 XED18 XED19))#define (bundle XED_H (add_net XED20 XED21 XED22 XED23 XED24 XED25 XED26 XED27))#define (bundle XED_H (add_net XED28 XED29 XED30 XED31))#define (bundle XEA (gap 7 (layer TOP BOTTOM INT1 INT2)) (nets XEA2 XEA3 XEA4 XEA5))#define (bundle XEA (add_net XEA6 XEA7 XEA8 XEA9 XEA10 XEA11 XEA12 XEA13 XEA14 XEA15 XEA16))#define (bundle YED_L (gap 7 (layer TOP BOTTOM INT1 INT2)) (nets YED0 YED1 YED2 YED3))#define (bundle YED_L (add_net YED4 YED5 YED6 YED7 YED8 YED9 YED10 YED11))#define (bundle YED_L (add_net YED12 YED13 YED14 YED15))#define (bundle YED_H (gap 7 (layer TOP BOTTOM INT1 INT2)) (nets YED16 YED17 YED18 YED19))#define (bundle YED_H (add_net YED20 YED21 YED22 YED23 YED24 YED25 YED26 YED27))#define (bundle YED_H (add_net YED28 YED29 YED30 YED31))#define (bundle YEA (gap 7 (layer TOP BOTTOM INT1 INT2)) (nets YEA2 YEA3 YEA4 YEA5))#define (bundle YEA (add_net YEA6 YEA7 YEA8 YEA9 YEA10 YEA11 YEA12 YEA13 YEA14 YEA15 YEA16))define (pair (nets BFS?+ BFS?- (gap 8)))define (pair (nets BCLK?+ BCLK?- (gap 8)))define (pair (nets BDX?+ BDX?- (gap 8)))define (pair (nets BDR?+ BDR?- (gap 8)))set average_pair_length onrule class POWER (width 14.0) (clearance 9 (type wire_wire)) rule class CVDD (width 18.0) (clearance 10 (type wire_wire)) rule class DIFF0 (width 10.0) (clearance 10 ) (limit_vias 1)rule class DIFF1 (width 10.0) (clearance 10 ) (limit_vias 1)rule class CLOCKS (width 12) (clearance 10 (type wire_wire)) (limit_vias 4)rule class PLL (width 10) (clearance 10 (type wire_wire)) (limit_vias 2)circuit class POWER (use_via medium_via) (priority 150) circuit class CVDD (use_via medium_via) (priority 150) circuit class CLOCKS (use_via medium_via) (priority 150)circuit class DIFF0 (use_via min_via) (priority 150) (match_net_length on (tolerance 101))circuit class DIFF1 (use_via min_via) (priority 150) (match_net_length on (tolerance 101))circuit class OTHER (use_via min_via)circuit class PLL (use_via min_via) (priority 200)direction TOP diagonaldirection INT1 orthogonaldirection INT2 orthogonaldirection BOTTOM diagonalcost side_exit freecost off_center freecost layer Top free (type length)cost layer Top free (type way)cost layer Int1 free (type length)cost layer Int1 forbidden (type way)cost layer Int2 free (type length)cost layer Int2 forbidden (type way)cost layer Bottom free (type length)cost layer Bottom free (type way)protect all viasprotect all wiresvia_at_smd offselect component U1select component U2select component U3select component U4select component U5select component U6select component U7select component U8select component U9select component U10fanout 1 (direction in_out) (max_len 350) (location anywhere) (pin_share on) (smd_share on) (via_share on) (share_len 305) (pin_type power)unselect all objectsselect component U3select component U4select component U5select component U6select component U7fanout 1 (smart_via_grid one_wire_between) (direction in_out) (max_len 250) (location anywhere) (pin_share off) (smd_share off) (via_share off) (pin_type all)unselect all objectsselect component U1select component U2fanout 1 (direction in_out) (max_len 250) (location anywhere) (pin_share off) (smd_share off) (via_share off) (pin_type all)unselect all objectsbus diagonalset diagonal_mode alwaysset dynamic_pinswap on#select all bundleselect all paircost via highroute 40protect selected_wiresunselect all objectstax way 4#forget bundle XED_L XED_H XEA YED_L YED_H YEA#set diagonal_mode oncost via mediumroute 3cost via highroute 20clean 2tax way 8tax via 4route 25 10clean 2route 25 30clean 4route 1route 30 65clean 8write wire $\packer_a.wcenterspread (extra 20 1)miter (pin) (tjunction) (bend) (style diagonal)criticwrite wire $\packer_a.mwrite session $\packer_a.sesreport status $\packer_a.sts
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# SHIPHT Do
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tax squeeze .2fanout 5 (max_len -1)(pin_type active)(pin_share on)(via_share on)(share_len 100)tax squeeze 1# limit way 300# rule layer internal1(limit_way 250)# cost way 50# tax way 4# cost layer sig2 50 (type way)tax cross 1.2tax squeeze .5####################### Startroute 10if (complete_wire < 100) then (clean 2)#### Route phase 1setexpr count (3)while (count >0 && complete_wire < 100) (setexpr comp_rate (complete_wire)route 5 11if (complete_wire < 100 && complete_wire > comp_rate) then (setexpr count (count - 1) ) else (setexpr count (0)) )#### Route phase 2if (complete_wire < 100) then (clean 2)setexpr count2 (5)while (count2 >0 && complete_wire < 100) ( setexpr comp_rate2 (complete_wire)route 5 16if (complete_wire > comp_rate2) then (setexpr count2 (count2 - 1) ) else (filter 5limit cross 1route 10 16clean 2setexpr count2 (0) ) ) #### Route phase 3if (complete_wire < 100) then (clean 2)setexpr count3 (10)while (count3 >0 && complete_wire < 100) ( setexpr comp_rate3 (complete_wire)route 10 16if (complete_wire > comp_rate3) then (setexpr count3 (count3 - 1) ) else (filter 3limit cross 4route 10 16clean 2setexpr count3 (0) ) )#### Route phase 4if (complete_wire < 100) then (clean 4)setexpr count4 (100)while (count4 >0 && complete_wire < 100) ( setexpr comp_rate4 (complete_wire)route 5 16if (complete_wire > comp_rate4) then (setexpr count4 (count4 - 1) ) else (filter 5limit cross 0route 20 16clean 5setexpr count4 (0) ) )##### Final Cleanupclean 5
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