If the watchdog is configured to reset the device, then a WDCR overflow or writing the incorrect value to the WDCR[WDCHK] bits resets the device and sets the watchdog flag (WDFLAG) in the WDCR register. After a reset, the program can read the state of this flag to determine the source of the reset. After reset, the WDFLAG should be cleared by software to allow the source of subsequent resets to be determined. Watchdog resets are not prevented when the flag is set.
WDFLAG Watchdog reset status flag bit 0 The reset was caused either by the XRS pin or because of power-up. The bit remains latched until you write a 1 to clear the condition. Writes of 0 are ignored. 1 Indicates a watchdog reset (WDRST) generated the reset condition. .