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2.5.3 Arbitration Between the CPU and the DMA Controller
As shown in Figure 2–7, Figure 2–8, Figure 2–9, and Figure 2–10, the peripheral bus controller performs arbitration between the CPU and the DMA controller for the peripheral bus. Like internal data access, the PRI bits in the DMA controller determine the priority between the CPU and the DMA controller. If a conflict occurs between the CPU (via the data memory controller) the lower priority requester is held off until the higher priority requester completes all accesses to the peripheral bus controller. The peripheral bus is arbitrated as a ingle resource, so the lower priority resource is blocked from accessing all peripherals, not just the one accessed by the higher priority requester.
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